Multiprocessor system architecture

Claim 2

1 Multiprocessor system architecture where a first and a second processor at least are provided with a first and a second autonomous bus respectively and the two busses can be selectively connected each other and where the two processors communicate each other through messages stored into mailboxes included in a memory resource, connected to one of said bus, characterized by that said system comprises: -an interruption signal generator (27) for generating a first interruption signal sent to the first processor and a second interruption signal sent to the second processor, said generator having connections to said first and second bus, said generator being set in a first status, where said interruption signal is present, by signals applied to said second bus by said second processor and being set in a second status, where said first signal is not present, by signals applied to said first bus by said first processor, said generator being set in a third status, where said second interruption signal is present, by signals applied to said first bus by said first processor and being set in a fourth status, where said second signal is not present by signals applied to said second bus by said second processor.

Claim 3

2 System architecture as per claim 1 further comprising first means (43) controlled by said first processor through said first bus, for reading, through said first bus and the connection of said generator to said first bus, the status (third or fourth) of said generator.

Claim 4

3 System architecture as per claim 2 further comprising second means (42), controlled by said second processor, through said second bus, for reading through said second bus and the connection of said generator to said second bus, the status (first or second) of said generator.

Claim 5

4 In system architecture as per claim 3, communication method between said first and second processor, consisting of the following steps:

Claim 6

-verification by said first processor that said generator is in said fourth status,

Claim 7

-verification by said first processor that said generator is in said fourth status,

Claim 8

-writing by said first processor, in a mailbox coupled to said second processor, of a message intended for said second processor, without locking of the mailbox

Claim 9

-writing by said first processor, in a mailbox coupled to said second processor, of a message intended for said second processor, without locking of the mailbox

Claim 10

-set of said generator in said third status by said first processor and consequent generation of said second interruption signal,

Claim 11

-set of said generator in said third status by said first processor and consequent generation of said second interruption signal,

Claim 12

-reading out, by said second processor, of said mailbox compled to the second processor, without locking of said mailbox, as answer to said second interruption signal,

Claim 13

-reading out, by said second processor, of said mailbox compled to the second processor, without locking of said mailbox, as answer to said second interruption signal,

Claim 14

-set of said generator in said fourth status by said second processor.

Claim 15

-set of said generator in said fourth status by said second processor.

Claim 16

5 In a system architecture as per claim 3 a method for message exchange between said first and second processor and for message preemption consisting in the following steps: a) verification by said first processor that a mailbox coupled to said second processor is available and locking of the same. b) writing by said first processor of a message intended for said second processor in said mailbox, c) setting free of said mailbox coupled to said second processor by said first processor, d) set of said generator in said third status by said first processor and consequent generation of said second interruption signal. e) verification by said second processor that said mailbox coupled to said second processor is available and locking of the said mailbox in response to said second interruption signal, f) reading out by said second processor of said mailbox, g) set of said generator in said fourth status by said second processor, h) setting free (liberation) of said mailbox simultaneously with or after previous step (g) by said second processor, i) verification by said first processor at any instant after steps d) that said generator is in said third status and in the affermative case j) Verification by said first processor that said mailbox is unlocked and in the affermative case k) preemption by said first processor of the message already written with a new message and I) setting free (unlocking) of said mailbox by said first processor.