A small contactless ram cell

Claim 2

An MOS transistor integrated in a substrate of a first conductivity type contiguous source, drain and channel regions in said substrate wherein said source and drain regions are doped to a second conductivity type and wherein each of said source, drain and channel regions has an area which is smaller than the area of the smallest contact window which can be formed in the process used to form the transistor; a gate electrode overlying said channel region and insulated therefrom; and doped polysilicon source and drain electrodes in electrical contact with said source and drain regions.

Claim 3

A device as defined in claim 1 wherein said gate is self-aligned on all but one edge of the perimeter of said channel region and extends out to and assumes the shape of a contact pad having sufficient area to encompass a contact window or post type via.

Claim 4

A device as defined in claim 1 wherein said source and drain electrodes extend out to and assume the shape of contact pads having sufficient area to encompass a contact window or post type via.

Claim 5

A device as defined in claim 3 wherein said source and drain electrodes are self-aligned with said source and drain regions on at least two edges.

Claim 6

A device as defined in claim 1 wherein said gate electrode and said polysilicon source and drain conductors are formed out of the same layer of deposited polysilicon such that they are at the same mask level of the MOS transistor structure.

Claim 7

A device as defined in claim 5 wherein said gate electrode and said source and drain electrodes are in each electrical contact with a layer of silicide formed on each said electrode.

Claim 8

A device as defined in claim 6 wherein said silicide is self-aligned with the edges of said electrodes..

Claim 9

A MOS transistor comprising: a substrate dopes with impurities of a first type within an isolation island; source and drain regions located in said isolation island and doped with impurities of a second type and connected by a channel region; doped polysilicon source and drain electrodes in electrical contact with said source and drain regions; a polysilicon gate electrode located over said substrate between said source and drain regions and insulated therefrom and each said gate, source and drain electrode having an area within said isolation island which is smaller than the smallest contact window which can be made with the process used to make the transistor; a self-aligned layer of silicide overlying each said polysilicon electrode and in electrical contact therewith to lower the resistance thereof; and wherein each of said gate source and drain electrodes extends outside of said isolation island to make electrical contact with another structure.

Claim 10

A MOS transistor comprising: a substrate dopes with impurities of a first type within an isolation island; source and drain regions located in said isolation island and doped with impurities of a second type and connected by a channel region; doped polysilicon source and drain electrodes in electrical contact with said source and drain regions; a polysilicon gate electrode located over said substrate between said source and drain regions and insulated therefrom and each said gate, source and drain electrode having an area within said isolation island which is smaller than the smallest contact window which can be made with the process used to make the transistor; a self-aligned layer of silicide overlying each said polysilicon electrode and in electrical contact therewith to lower the resistance thereof; and wherein each of said gate source and drain electrodes extends outside of said isolation island to make electrical contact with another structure.

Claim 11

A static RAM cell comprising at least six MOS transistors as defined in claim 5 having their gate source and drain electrodes interconnected on the same polysilicon level from which said gate, source and drain electrodes were formed in such a manner as to form any static RAM cell circuit.

Claim 12

A static RAM cell as defined'in claim 9 further comprising a layer of silicide formed over said polysilicon electrodes and interconnects.

Claim 13

A static RAM cell as defined in claim 10 wherein each transistor is constructed in an island in said substrate which is electrically isolated from the rest of the substrate.

Claim 14

A static RAM cell as defined in claim 10 wherein said gate electrode is self-aligned with the edges of the source and drain regions.

Claim 15

The cell of claim 12 wherein each said island is defined by field oxide regions which extend through a layer of epitaxially grown silicon formed over a substrate.

Claim 16

A static RAM cell comprising: first, second, third, fourth, fifth and sixth MOS transistors as defined in claim t, each transistor being formed in an island of silicon formed in said substrate so as to be electrically isolated from the rest of said substrate, and each transistor having gate, source and drain electrodes formed from the same layer of doped polysilicon; a first shared node of doped polysilicon which is an extension of an electrically connects the gate electrodes of said first and fifth transistors and the source electrodes of said third and fourth transistors and the drain electrode of said second transistor; a second shared node of doped polysilicon which is an extension of and electrically connects the gate electrodes of said second and fourth transistors and the source electrodes of said fifth and sixth transistors a and the drain electrode of said first transistor; a ward line interconnection of doped polysilicon which is an extension of and electrically connects the gate electrodes of said third and sixth transistors; a power supply interconnection of doped polysilicon which is an extension of and electrically connects individually to the drain electrodes of said fourth and fifth transistors; a reference voltage interconnection of doped polysilicon which is an extension of and electrically connects individually to the source electrodes of said first and second transistors; and first and second bit line interconnections which are extensions of and which electrically connect to the drain electrodes of said third and sixth transistors respectively.

Claim 17

A static RAM cell as defined in claim 14 further comprising a layer of silicide formed over all said polysilicon electrodes and interconnects.

Claim 18

A static RAM cell as defined in claim 15 where at least one of said polysilicon electrodes extends to a region outside the island of its associated transistor and assumes the geometry of a contact pad which has an area which is large enough to contain a contact window or post type via.

Claim 19

An array of static RAM cells consisting of a plurality of the cells as defined in claim 15 arranged into rows and columns wherein the gate electrodes of the third and sixth transistors of all the cells in each column are a shared polysilicon contact and wherein the polysilicon drain electrodes of said third and sixth transistors in cells in the same row and at least some of the adjacent columns are shared.

Claim 20

An array of static RAM cells consisting of a plurality of the cells as defined in claim 15 arranged into rows and columns wherein the gate electrodes of the third and sixth transistors of all the cells in each column are a shared polysilicon contact and wherein the polysilicon drain electrodes of said third and sixth transistors in cells in the same row and at least some of the adjacent columns are shared and wherein the polysilicon drain electrodes of the fourth transistor in adjacent cells in the same column in a first plurality of adjacent rows are shared and wherein the polysilicon source electrodes of the second transistors in adjacent cells in the same column in said first plurality of adjacent rows are shared and wherein the polysilicon source electrodes of the first transistors in adjacent cells in the same column in a second plurality of rows are shared and wherein the polysilicon drain electrodes of adjacent cells in the same column in said second plurality of adjacent rows are shared.

Claim 21

An array of static RAM cells consisting of a plurality of the cells as defined in claim 15 arranged into rows and columns wherein the gate electrodes of the third and sixth transistors of all the cells in each column are a shared polysilicon contact and wherein the polysilicon drain electrodes of the fourth transistors in adjacent cells in the same column in a first plurality of adjacent rows are shared and wherein the polysilicon source electrodes of the second transistors in adjacent cells in the same column in said first plurality of.adjacent rows are shared and wherein the polysilicon source electrodes of the first transistors in adjacent cells in the same column in a second plurality of rows are shared and wherein the polysilicon drain electrodes of adjacent cells in the same column in the said second plurality o adjacent rows are shared.

Claim 22

A process for forming MOS transistors of the type defined in claim 1 and bipolar transistors on the same integrated circuit substrate comprising the steps of: forming isolated islands of silicon of the proper conductivity for all bipolar and MOS transistors to be formed in said substrate; forming a layer of gate insulating material over only the MOS islands and only over that portion of the MOS island over which the gate electrodes will be formed; forming a plurality of transistor surface electrodes having top surfaces parallel to said substrate and side surfaces normal to substrate surface. said electrodes being formed out of the same layer of polysilicon which has been properly doped with the correct type of impurities in the regions where electrodes are to be formed, said electrodes to serve as the gate, source, drain, emitter, collector and base electrodes of the transistors being formed; doping said substrate to form source and drain regions in electrical contact with said source and drain electrodes and aligned on one edge with the edges of said gate electrodes; forming a layer of insulating material over all exposed silicon except said top surfaces of said electrodes; and heating the structure long enough and at an appropriate temperature to cause outdiffusion of impurities from said electrodes so as to form emitter regions in said substrates, and collector, source and drain contact regions in said substrate.

Claim 23

The process of claim 20 further comprising a step of forming a layer of silicide over said polysilicon electrodes and self-aligned with the edges thereof and wherein the step of'doping said substrate include the steps of doping the source and drain regions of MOS islands having N doped poly electrodes of N types to form an N channel transistor and doping the source and drain regions of MOS islands having P doped electrodes of P type to form a P channel transistor while simultaneously allowing the P type impurities to enter the substrate in bipolar NPN transistor islands.

Claim 24

A process of forming CMOS transistors of the type defined in claim 1 and bipolar transistors on the same integrated circuit substrate in which there have been formed suitable buried layers, a layer of epitaxially grown silicon and electrically isolated regions of said epitaxially grown silicon comprising the steps of: (1) doping the base regions and predetermined MOS active regions with impurities of a conductivity type selected to create the desired conductivity for a base region for selected types to bipolar transistor and for a channel region for a selected type of MOS transistor; (2) forming a gate oxide layer over a predetermined portion of all MOS isolation islands while preventing oxidation of the isolation regions for all bipolar devices; (3) depositing a layer of polysilicon over the surface of said substrate; (4) doping selected areas of said polysilicon with N type impurities and other selected areas with P type impurities; (5) etching the doped polysilicon area using etched nitride as an etch mask so as to form source and drain contacts and gate contacts for MOS devices and emitter, base and collector contacts for bipolar devices; (6) heating the structure for a time sufficient to form emitter regions and source, drain and collector contacts; (7) doping regions in said epitaxial layer adjacent the gate contacts of a first selected group of MOS devices with P type impurities and allowing said impurities to enter exposed regions of the substrate in all NPN bipolar transistor islands to lower the base resistance and doping regions in said epitaxial layer adjacent the gate contacts of a second selected groups of MOS devices with N type impurities; (8) forming an insulating layer over the epitaxial silicon and the edges of the polysilicon contacts; (9) selectively etching off said nitride etch mask from the tops of said polysilicon contacts; and (10) forming a layer of silicide over said polysilicon contacts and self-aligned with the edges thereof.

Claim 25

The process of claim 22 wherein step 5 comprises the steps of: depositing a layer of nitride over the polysilicon layer; depositing a layer of photoresist on said nitride layer; exposing selected areas of said photoresist to radiation through a mask to harden the resist in selected areas wherein the areas exposed are selected so at to leave nitride over the poly at the location of the emitter, base, and collector contacts for the bipolar devices and the gate contact and the source and drain contacts of the MOS devices; dissolving the unhardened resist: etching away the nitride not protected by resist; and etching away the polysilicon not protected by nitride.

Claim 26

The process of claim 23 wherein the step 8 comprises the steps of: thermally growing silicon dioxide in the regions exposed by the etching of the polysilicon; removing the remaining nitride left over from the polysilicon etch step to expose the tops of the polysilicon contacts; depositing a layer of refractory metal capable of forming a silicide on the structure; heat treating the structure to form silicide wherever the metal is in contact with polysilicon; and removing the unreacted metal.