§
Luxuse
Patent Intelligence
Sign In
Patent EP0200440A2 successfully refreshed from Google Patents.
← Back to Patent Explorer
EP0200440A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Electronic circuit for connecting a processor to a high-capacity memory

Assignee: Olivetti SpA
•
Filing: 1986-04-18
•
Granted: —
•
Expires: 2006-04-18
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract The electronic circuit connects a processor (20) to a high-capacity memory (21) of 1 Megabyte. The processor (20) may be of the 8 bit type, with a 16 bit address bus (AO-A15). The memory is subdivided into 256 segments each having a capacity of 4 Kbytes which can be directly addressed by the processor by means of 12 (A0-A11) of the 16 lines of the address bus. An auxiliary RAM (30) is interposed between the processor (20) and the 1 Mbyte memory (21) and comprises sixteen 8 bit registers (RO-R15), which can be addressed by means of the other four lines (A12-A15) of the address bus. By means of the 8 bit data bus (DO-D7), the 16 registers of the RAM (30) store the numbers of those 16 segments out of the 256 segments of the 1 Mbyte memory, which from time to time are connected to the processor. In this way the processor (20), while being able to address only 64 Kbytes of memory at a time, has the whole of the 1 Mbyte memory available. The circuit can be applied to data processing and word processing units and electronic typewriters.

Inventors

  • 👤 Walter Cerutti

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-06 13:52
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 177 words
An electronic circuit for connecting a processor (20) to a segmented high-capacity memory (21), in which the processor comprises a data bus (DO-D7) having a given number of channels for transferring data from and to said memory and an address bus having a given number of channels for addressing said memory, characterised in that the memory segments (SEG.O-SEG.255) each have a capacity such as can be directly addressed by means of a first portion (AO-All) of the address bus, by an auxiliary memory (30) interposed between the processor (20) and the high-capacity memory (21) and comprising a number of registers (RO-RI5) equal to the number of segments of the high-capacity memory which can be connected at one time to the processor, that the registers are capable of being addressed by means of a second portion (AI2-A15) of the address bus for addressing one of the segments in accordance with the contents of the addressed register, and that the contents of the registers (R0-R15) can be modified by the processor (20) by way of the data bus (DO-D7).
Claim 2
Dependent Claim 177 words
An electronic circuit for connecting a processor (20) to a segmented high-capacity memory (21), in which the processor comprises a data bus (DO-D7) having a given number of channels for transferring data from and to said memory and an address bus having a given number of channels for addressing said memory, characterised in that the memory segments (SEG.O-SEG.255) each have a capacity such as can be directly addressed by means of a first portion (AO-All) of the address bus, by an auxiliary memory (30) interposed between the processor (20) and the high-capacity memory (21) and comprising a number of registers (RO-RI5) equal to the number of segments of the high-capacity memory which can be connected at one time to the processor, that the registers are capable of being addressed by means of a second portion (AI2-A15) of the address bus for addressing one of the segments in accordance with the contents of the addressed register, and that the contents of the registers (R0-R15) can be modified by the processor (20) by way of the data bus (DO-D7).
Claim 3
Dependent Claim 65 words
An electronic circuit according to claim 1, wherein the data bus (Do-D7) has R bits and the address bus (AO-A15) has 16 bits by means of which 64 Kbytes of the high-capacity memory (21) can be addressed, characterised in that each of the segments (SEG.O-SEG.255) has a capacity of 4 Kbytes and that the first portion of the address bus comprises 12 address bits (AO-All).
Claim 4
Dependent Claim 31 words
An electronic circuit according to claim 2, characterised in that the auxiliary memory (30) comprises 16 registers (R0-R15) and that the portion of the address bus comprises 4 address bits (AI2-A15).
Claim 5
Dependent Claim 65 words
An electronic circuit according to claim 3, characterised in that the high-capacity memory (21) is subdivided into 256 segments (SEG.O-SEG.255) and that each of the registers (RO-R15) comprises eight memory cells, each connected to a line of the data bus (DO-D7), whereby the processor (20) can determine from time to time which of the 256 segments is to be associated with each of the registers.
Claim 6
Dependent Claim 27 words
An electronic circuit according to claim 4, characterised by a decoder (31) interposed between the second portion (A12-A15) of the address bus and the auxiliary memory (30).

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag