Digital signal reproducing circuit

Claim 2

A digital signal reproducing circuit comprising: a wave-shaping circuit (16) for converting highfrequency signals comprising digital signals modulated by the predetermined modulation system into binary signals; a phase locked loop circuit means (17, 18) for generating a bit synchronizing clock synchronized in phase to the leading edge of said binary signal produced by said wave-shaping circuit (16); and data processor means (26) for producing digital signals from said binary signal under a control of said bit synchronizing clock generated by said phase locked loop circuit means (17, 18); CHARACTERIZED IN THAT said digital signal reproducing circuit further comprises: first and second frequency divider (19, 20), first and second pattern detector means (21, 22), a synchronization means (23, 24) and a timing signal generation means (25), and wherein: said phase locked loop circuit means (17, 18) include a first phase locked loop circuit means (17) for generating a first bit synchronizing clock synchronized in phase to the leading edge of said binary signal and a leading edge detection data synchronized to said first bit synchronizing clock and a second phase locked loop circuit means (18) for generating a second bit synchronizing clock synchronized in phase to the trailing edge of said binary signal and a trailing edge detection data synchronized to said second bit synchronizing clock; said first and second frequency divider means (19, 20) respectively divide said first and second bit synchronizing clocks; said first and second pattern detector means (21, 22) respectively detect signal patterns specified in said binary signal; said synchronization-means (23, 24) synchronize the output of said first and second frequency divider means (19, 20) after the signal patterns are detected by said first pattern detector means (21) or said second pattern detector means (22); said timing signal generation means (25) detect the phase difference of each output of said first and second frequency divider means (19, 20) after synchronized by means of said synchronization means (23, 24) and generate timing signals on the basis of the phase difference and said second data signal; and said data processor means (26) produce digital signals corrected by said timing signal and said first data signal.

Claim 3

A circuit as set forth in claim 1, wherein said first and second frequency divider means (19, 20) divide said first and second bit synchronizing clocks into four, respectively.

Claim 4

A circuit as set forth in claim 1, wherein said first and second pattern detector means (21, 22) detect said signal patterns of two times the minimum inversion period of said binary signal, respectively.

Claim 5

A circuit as set for the in claim 1, wherein said first and second pattern detector means (21, 22) detect said signal patterns of two times the maximum inversion period of said binary signal, respectively.

Claim 6

A circuit as set forth in claim 1, wherein said synchronization means (23, 24) include a latch circuit (62, 63, 64, 65) and a gate circuit (50, 51, 54, 55) connected to said first and second frequency divider means (19, 20).

Claim 7

A circuit as set forth in claim 5, wherein said synchronization means (23, 24) has a first latch circuit (62, 63) connected to said first frequency divider (19) and a second latch circuit (64, 65) connected to said second frequency divider means (20), the outut data of said first latch circuit (62, 63) is preset to said second frequency divider means (20), the output data of second latch circuit (64, 65) is preset to said first frequency divider means (62, 63).

Claim 8

A digital signal reproducing circuit comprising: a wave-shaping circuit (16) for converting highfrequency signals comprising digital signals modulated by the predetermined modulation system into binary signals; a phase locked loop circuit means (17, 18) for generating a bit synchronizing clock synchronized in phase to the leading edge of said binary signal produced by said wave-shaping circuit (16); and data processor means (26) for producing digital signals from said binary signal under a control of said bit synchronizing clock generated by said phase locked loop circuit means (17, 18); CHARACTERIZED IN THAT said digital signal reproducing circuit further comprises: first and second frequency divider means (19, 20), a pattern detector means (21), a synchronization means(24) and a timing signal generation means (25), and wherein: said phase locked loop circuit means (17, 18) includes a first phase locked loop circuit means (17) for generating a first bit synchronizing clock synchronized in phase to the leading edge of said binary signal and a leading edge detection data synchronized to said first bit synchronizing clock and a second phase locked loop circuit means (18) for generating a second bit synchronizing clock synchronized in phase to the trailing edge of said binary signal and a trailing edge detection data synchronized to said second bit synchronizing clock; said first and second frequency divider means (19, 20) respectively divide said first and second bit synchronizing clocks; said pattern detector means (21) detect signal patterns specified in said binary signal; said synchronization means (24) synchronize the output of said first and second frequency divider means (19, 20) after the signal patterns are detected by said pattern detector means (21); said timing signal generation means (25) detect the phase difference of each output of said first and second frequency divider means (19, 20) after synchronized by means of said synchronization means (23, 24) and generates timing signals on the basis of the phase difference and said second data signal; and said data processor means (26) produce digital signals corrected by said timing signal and said first data signal. 8. A circuit as set forth in claim 7, wherein said first and second frequency divider means (19, 20) divide said first and second bit synchronizing clocks, respectively, into four.

Claim 9

9 . A circuit as set forth in claim 7, wherein said pattern detector means (21) detect signal patterns of two times the minimum inversion period of said binary signal.

Claim 10

A circuit as set forth in claim 7, wherein said pattern detector means (21) detect signal patterns of two times the maximum inversion period of said binary signal, respectively.

Claim 11

A circuit as set forth in claim 7, wherein said synchronization means (24) include a gate circuit (50, 51) connected to said first frequency divider means (19) and a latch circuit (64, 65) connected to said second frequency divider means (29).

Claim 12

A circuit as set forth in claim 11, wherein an output data of said latch circuit (64, 65) in said synchronization means (24) is preset to said first frequency divider means (19).

Claim 13

1 3. A digital signal reproducing circuit comprising: a wave-shaping circuit (16) for converting highfrequency signals comprising digital signals modulated by the predetermined modulation system into binary signals; a phase locked loop circuit means (81) for generating a bit synchronizing clock synchronized in phase to the leading edge of said binary signal produced by said wave-shaping circuit (16); and data processor means (84) for producing digital signals from said binary signal under a control of said bit synchronizing clock generated by said phase locked loop circuit means (81); CHARACTERIZED IN THAT said digital signal reproducing circuit further comprises: pattern detector means (82) and a phase error detecting means (83), and wherein: said phase locked loop circuit means (81) includes a phase comparator (85) for comparing in phase said binary signal outputted from said wave-shaping circuit (16) with said bit synchronizing clock at the specified edge timing of said binary signal, an oscillator circuit (87) for generating a master clock on the basis of the output of said phase comparator (85) and a frequency divider circuit (88) for dividing said master clock and for generating a bit synchronizing clock in synchronized with said binary signal; said phase error detecting means (83) include a frequency divider (88, 89) and a register (93, 94) and output a correction signal for correcting said binary signal after the specified signal pattern detected by said pattern detector means (82); and said data processor means (84) produce digital signals corrected by said timing signal and said first data signal.

Claim 14

1 3. A digital signal reproducing circuit comprising: a wave-shaping circuit (16) for converting highfrequency signals comprising digital signals modulated by the predetermined modulation system into binary signals; a phase locked loop circuit means (81) for generating a bit synchronizing clock synchronized in phase to the leading edge of said binary signal produced by said wave-shaping circuit (16); and data processor means (84) for producing digital signals from said binary signal under a control of said bit synchronizing clock generated by said phase locked loop circuit means (81); CHARACTERIZED IN THAT said digital signal reproducing circuit further comprises: pattern detector means (82) and a phase error detecting means (83), and wherein: said phase locked loop circuit means (81) includes a phase comparator (85) for comparing in phase said binary signal outputted from said wave-shaping circuit (16) with said bit synchronizing clock at the specified edge timing of said binary signal, an oscillator circuit (87) for generating a master clock on the basis of the output of said phase comparator (85) and a frequency divider circuit (88) for dividing said master clock and for generating a bit synchronizing clock in synchronized with said binary signal; said phase error detecting means (83) include a frequency divider (88, 89) and a register (93, 94) and output a correction signal for correcting said binary signal after the specified signal pattern detected by said pattern detector means (82); and said data processor means (84) produce digital signals corrected by said timing signal and said first data signal.

Claim 15

A circuit as set forth in claim 13, wherein said phase locked loop circuit means (81) further include a phase comparator means (85) for comparing said binary signals with said bit synchronization signals at the timing of the leading edges of said binary signals.

Claim 16

A circuit as set forth in claim 14, wherein said phase locked loop circuit means (81) further include a phase comparator means (85, 105) for comparing said binary signals with said bit synchronization signals at the timing of the trailing edges of said binary signals.

Claim 17

A circuit as set forth in claim 15, wherein said phase locked loop circuit means (81) further generate leading edge detection pulses of said binary signal.

Claim 18

A circuit as set forth in claim 15, wherein said phase locked loop circuit means (81) further generate trailing edge detection pulses of said binary signal.

Claim 19

A circuit as set forth in claim 13, wherein said phase error detecting means (83) generate a first phase difference detection signal and a second phase difference detection signal in different phases by dividing said master clock, and further generate a third phase difference detection signal and a fourth phase difference detection signal in different phases by further dividing said first phase difference detection signal, and wherein said register (93, 94) outputs said correction signal after said first, second, third and fourth phase difference detection signals are inputted and the specified patterns are detected by said pattern detector means (82).

Claim 20

A circuit as set forth in claim 14, wherein said pattern detector means (82) detect that a space between leading edges of said binary signal is two times the minimum inversion period.

Claim 21

A circuit as set forth in claim 14, wherein said pattern detector means (82) detect that a space between leading edges of said binary signal is two times the maximum inversion period.

Claim 22

2 1. A circuit as set forth in claim 15, wherein said pattern detector means (82) detect that a space between trailing edges of said binary signal is two times the minimum inversion period.

Claim 23

A circuit as set forth in claim 15, wherein said pattern detector means (82) detects that a space between trailing edges of said binary signal is two times the maximum inversion period.