EP0098349A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Frequency detecting circuit for digital information reproducing system
Assignee: Toshiba Corp
•
Filing: 1983-03-25
•
Granted: —
•
Expires: 2003-03-25
Abstract
Abstract A circuit is disclosed which is applied for a ditial audio disk (DAD) system for detecting a maximum inverting period of a digital audio signal (102) optically read out from the DAD. The audio signal is prestored in the DAD so as to have the maximum and minimum inverting periods specially set by an eighteen to fourteen modulation (EFM). The detection circuit includes an edge detector (104) for detecting pulse edges of the digital audio signal (102), a counter (106) for counting pulse edge intervals on the basis of a modulating clock signal (108), a counter type register (114), and a comparator (112). When the register contents of the counter type register (114) is smaller than the count value of the counter (106), the comparator (112) produces a pulse signal (118) by which said register (114) updates the contents of the register by "1". Repeating this operation, a maximum inverting period value of the digital audio signal (102) is obtained in a fixed period of time.
Inventors
- 👤 Meisei Nishikawa
- 👤 Yukio Nakamura
- 👤 Tadashi Kojima
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 05:13
CPC Classifications
G; G11; G11B; G11B5/00; G11B5/02; G11B5/09; G11B27/00; G11B27/10; G11B27/34; G11B19/00; G11B19/20; G11B19/28; G11B20/00; G11B20/10; G11B20/10527; G11B20/14; G11B20/1403; G11B20/1423; G11B20/18; G11B20/1806; G11B7/00; G11B7/004; G11B7/005; G11B2220/00; G11B2220/20
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
188 words
A circuit for detecting one of the upper and lower period limits in demodulating a digital information signal (102), which is applied to a reproduction system for reproducing an information signal digitally prestored in a recording medium (54) so as to satisfy the upper and lower inverting period limits preset according to a given modulation system, said circuit comprising: counter means (106, 150, 152, 174) for receiving a digital information signal (102), for counting a length of time duration during which the information signal (102) continuously holds its signal level at a given logic level, and for producing the count result data (110) corresponding to said length of time duration; and register means (114, 136) connected to said counter means (106, 150, 152, 174) for storing therein a register value corresponding to a period value, for applying a compensating operation of a unit value to said first register value to form a new register value, and for repeating said new register value forming operation to finally produce period value data (120) equivalent to one of the upper and lower inverting period values of said digital information signal (102).
Claim 2
Dependent Claim
188 words
A circuit for detecting one of the upper and lower period limits in demodulating a digital information signal (102), which is applied to a reproduction system for reproducing an information signal digitally prestored in a recording medium (54) so as to satisfy the upper and lower inverting period limits preset according to a given modulation system, said circuit comprising: counter means (106, 150, 152, 174) for receiving a digital information signal (102), for counting a length of time duration during which the information signal (102) continuously holds its signal level at a given logic level, and for producing the count result data (110) corresponding to said length of time duration; and register means (114, 136) connected to said counter means (106, 150, 152, 174) for storing therein a register value corresponding to a period value, for applying a compensating operation of a unit value to said first register value to form a new register value, and for repeating said new register value forming operation to finally produce period value data (120) equivalent to one of the upper and lower inverting period values of said digital information signal (102).
Claim 3
Dependent Claim
80 words
The circuit according to claim 1, characterized by further comprising comparator means (112, 132), connected to said counter means (106, 150, 152, 174) and said register means (114, 136), for comparing said count data (110, 110b, 162, 178) with said register contents data (116, 138) of said register means (114, 136) to generate an output signal (118, 134), thereby causing said register means (114, 136) to perform said new period forming operation in response to said output signal (118, 134).
Claim 4
Dependent Claim
70 words
The circuit according to claim 2, characterized by further comprising detector means (104) connected to said counter means (106, 150, 152, 174), for receiving said information signal (102) to detect level changing points of said information signal (102) between a first logic level and a second logic level, and for supplying a detection signal (107, 126) representing said logic level changing points to said counter means (106, 150, 152, 174).
Claim 5
Dependent Claim
48 words
The circuit according to claim 3, characterized in that said counter means (106, 150, 152, 174) receives a reference pulse signal (108) and said detection signal (107, 126) to count a time interval between said logic level changing points on the basis of said reference pulse signal (108).
Claim 6
Dependent Claim
87 words
The circuit according to claim 2, characterized by further comprising a logic operation element means (124) connected to said counter means (106), for receiving a reference pulse signal (108) and a digital information signal (102) changing between first and second logic levels, and for detecting a time period that a signal level of said information signal (102) is continuously held at one of said first and second logic levels to supply a detection signal (126) representing one of the logic level duration to said counter means (106).
Claim 7
Dependent Claim
85 words
The circuit according to claim 2, characterized in that said counter means includes a counter circuit (106) of n bit (n is a positive integer) which divides the count result data of n bit into first count result data (110a) corresponding to the upper m bit (m: a positive interger, n > m) and the second count result data (110b) of n-m bit, and separately produces first and second data (110a, 110b) said second count result data (110b) being supplied to said comparator means (132).
Claim 8
Dependent Claim
108 words
The circuit according to claim 6, characterized by further comprising AND gate means (130), having a first input connected to said counter means (106), a second input connected to said comparator means (132), and an output connected to said register means (136), for receiving said first count result data (110a) and said output signal (134) at said first input and said second input thereof, respectively to logically sum said first count result data (110a) and said output signal (134), whereby the number of bits of said register means (136) is reduced to the n-m number of bits of second count result data (110b) from said counter means (106).
Claim 9
Dependent Claim
151 words
The circuit according to claim 3, characterized in that said counter means comprises: a first counter (150) which receives a reference pulse signal (108) and said detection signal (107) and counts a time interval between said logic level changing points on the basis of said reference pulse signal (108); an inverter (154) for receiving said reference pulse signal (108) to logically invert said reference pulse signal (108); a second counter (152) arranged in parallel with said first counter (150) and connected to said inverter (154), which receives a reference pulse signal (108) inverted by said inverter (154) and said detection signal (107), and counts a time interval between said logic level changing points on the basis of said inverted reference pulse signal; and adding means (160) connected to said first and second counters (150, 152), for receiving and adding output data (156, 158) from said first and second counters (150, 152).
Claim 10
Dependent Claim
150 words
The circuit according to claim 3, characterized in that said counter means comprises: a frequency divider (170) for receiving and frequency-dividing a reference pulse signal (108) into a signal with a frequency of 1/N (N: a positive integer); N-stage shift registers (172) connected to said frequency divider (170), which receives said reference pulse signal with the 1/N frequency, shifts sequentially said reference pulse signal to produce first, second, ..., Nth clock pulse signals; counters (174) of N arranged in parallel to each other, which receive said detection signal (107) from said detector means (104) and receive said first, second, ..., Nth clock pulse signals, respectively, to count time intervals between said logic level changing points on the basis of said first, second, ..., Nth clock pulse signals, respectively; and adding means (176) connected to said counters (174), for receiving and adding the output data from said counters (174) of N.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.