Patent EP0199374A2 successfully refreshed from Google Patents.
EP0199374A2
Expired / Lapsed
EP
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High-speed CMOS buffer with controlled slew rate
Assignee: LSI Corp
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Filing: 1986-02-06
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Granted: —
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Expires: 2006-02-06
Abstract
Abstract A high-speed CMOS output buffer reduces transient current surges and provides high output DC drive. The buffer includes a first and a second CMOS inverter connected in parallel. Each of the two CMOS inverters includes an N channel and a P channel transistor. The gates of the transistors in the first inverter are controlled by a first control inverter having a first selected switching threshold voltage. The gate of the P channel transistor in the second inverter is controlled by a second control inverter having a switching threshold voltage higher than that of the first control inverter. The gate of the N channel transistor in the second inverter is controlled by a third control inverter having a switching threshold voltage lower than that of the first control inverter.
Inventors
- 👤 Anthony Y. Wong
- 👤 Robert M. Walker, Iii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 17:07
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429; H03K5/00; H03K5/01; H03K5/02; H03K5/023
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
224 words
A CMOS output buffer comprising a first inverter having an input lead and an output lead and a first control inverter for receiving an input signal and for providing the complement of said input signal to said input lead of said first inverter, said first control inverter having a first selected switching threshold voltage, said CMOS output buffer being characterized by comprising: a second inverter comprising a first transistor having a gate, a source and a drain, and a second transistor having a gate, a source and a drain, said first and said second transistors having channels of opposite conductivity type, said drains of said first and said second transistors being connected to said output lead of said first inverter; a second control inverter for receiving said input signal and for providing the complement of said input signal to said gate of said first transistor, said second control inverter having a second selected switching threshold voltage; a third control inverter for receiving said input signal and for providing the complement of said input signal to said gate of said second transistor, said third control inverter having a third selected switching threshold voltage, wherein said second selected switching threshold voltage is greater than said first selected switching threshold voltage and said third selected switching threshold voltage is less than said first selected switching threshold voltage.
Claim 2
Dependent Claim
224 words
A CMOS output buffer comprising a first inverter having an input lead and an output lead and a first control inverter for receiving an input signal and for providing the complement of said input signal to said input lead of said first inverter, said first control inverter having a first selected switching threshold voltage, said CMOS output buffer being characterized by comprising: a second inverter comprising a first transistor having a gate, a source and a drain, and a second transistor having a gate, a source and a drain, said first and said second transistors having channels of opposite conductivity type, said drains of said first and said second transistors being connected to said output lead of said first inverter; a second control inverter for receiving said input signal and for providing the complement of said input signal to said gate of said first transistor, said second control inverter having a second selected switching threshold voltage; a third control inverter for receiving said input signal and for providing the complement of said input signal to said gate of said second transistor, said third control inverter having a third selected switching threshold voltage, wherein said second selected switching threshold voltage is greater than said first selected switching threshold voltage and said third selected switching threshold voltage is less than said first selected switching threshold voltage.
Claim 3
Dependent Claim
30 words
A CMOS output buffer as in Claim 1 wherein said first transistor is a P channel enhancement mode transistor and said second transistor is an N channel enhancement mode transistor.
Claim 4
Dependent Claim
61 words
A CMOS output buffer as in Claim 2 wherein said second control inverter comprises a P channel enhancement mode transistor and having a gate, a source, and a drain, and an N channel enhancement mode transistor having a gate, a source, and a drain, said drain of said P channel transistor being connected to said drain of said N channel transistor.
Claim 5
Dependent Claim
56 words
A CMOS output buffer as in Claim 3 wherein said third control inverter comprises a P channel transistor having a gate, a source, and a drain, and an N channel transistor having a gate, a source, and a drain, said drain of said P channel transistor being connected to said source of said N channel transistor.
References Cited (Backward Citations)
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