Data processing system

Claim 2

A data processing system for processing data in accordance with instruction words comprising: (A) instruction word memory means (301) for storing at least one instruction word given by one reading operation; (B) first instruction decoding means (302) connected to said instruction word memory means and adapted to arrange an instruction word read out of said memory means into an intermediate machine word having an orthogonal code; (C) memory means (303) connected to said first instruction decoding means; and (D) at least one microprogram memory means - (202) connected to said memory means and at least one second instruction decoding means - (2030-2035) for decoding a microinstruction, said first instruction decoding means extracting information in one-to-one correspondence to inputs of said second instruction decoding means from said instruction word and storing said information in said memory means, said second instruction decoding means being operative to invalidate outputs of said second instruction decoding means using a microinstruction outputted from said microprogram memory means.

Claim 3

A data processing system in which at least one of instruction words including operation information for specifying an operation to be executed is an instruction word including at least one piece of operand specifying information for identifying a location of a main memory (102) at which an operand is contained, said operand being processed in response to said instruction word, said system comprising: (A) instruction word memory means (301) for se- quentiaity, in general, searching and storing instruction words which are entered successively; (B) instruction decoding means (302, 502) connected to said instruction word memory means and adapted to detect positions of operation information and operand designating information included in an instruction word and extract the operation information and operand specifying information separately; and (C) memory means (303) connected to said instruction word memory means and having predetermined bit positions for storing the operation information and operand specifying information, said system being operative to extract operation information and operand specifying information included in said instruction word, 'arrange said information in said predetermined bit positions of said memory means, and implement processing in accordance with contents of said memory means.

Claim 4

A data processing system in which at least one of instruction words including operation information for specifying an operation to be executed is an instruction word including at least one piece of operand specifying information for identifying a location of a main memory (102) at which an operand is contained, said operand being processed in response to said instruction word, said system comprising: (A) instruction word memory means (301) for se- quentiaity, in general, searching and storing instruction words which are entered successively; (B) instruction decoding means (302, 502) connected to said instruction word memory means and adapted to detect positions of operation information and operand designating information included in an instruction word and extract the operation information and operand specifying information separately; and (C) memory means (303) connected to said instruction word memory means and having predetermined bit positions for storing the operation information and operand specifying information, said system being operative to extract operation information and operand specifying information included in said instruction word, 'arrange said information in said predetermined bit positions of said memory means, and implement processing in accordance with contents of said memory means.

Claim 5

A data processing system having a main memory (102) for storing instruction words which include operation information specifying operations to be executed, at least one of said instruction words being an instruction word including at least one piece of operand specifying information for identifying a location of said main memory containing an operand, said main memory having contents expressed in instruction words having at least two kinds of instruction formats of different instruction binary code even though instruction functions of said instruction words are equal, said system further having a data processor (20) for processing operand in response to said instruction words having at least two instruction formats, said data processor comprising: (A) instruction word memory means (301) which sequentially, in general, searchs and stores instruction words resumed successively from said main memory; (B) a plurality of instruction decoding means (302, 502) connected to said instruction word memory means and adapted to detect positions of operation information and operand specifying information included in an instruction word, and extract operation information and operand specifying information separately, said decoding means being in correspondence to a plurality of instruction formats of instruction words in said main memory; (C) a multiplexer (503, 603) for selecting one of outputs of said plurality of instruction decoding means; (D) control means (506) for controlling said multiplexer; and (E) a memory (303) connected to said multiplexer and having predetermined bit positions for storing operation code information and operand designating information, said system extracting operation information and operand designating information included in an instruction read out of said main memory, arranging said information in said predetermined bit positions in said memory, and implementing processing in accordance with contents of said memory.

Claim 6

A data processing system having a main memory (102) for storing instruction words which include operation information specifying operations to be executed, at least one of said instruction words being an instruction word including at least one piece of operand specifying information for identifying a location of said main memory containing an operand, said main memory having contents expressed in instruction words having at least two kinds of instruction formats of different instruction binary code even though instruction functions of said instruction words are equal, said system further having a data processor (20) for processing operand in response to said instruction words having at least two instruction formats, said data processor comprising: (A) instruction word memory means (301) which sequentially, in general, searchs and stores instruction words resumed successively from said main memory; (B) a plurality of instruction decoding means (302, 502) connected to said instruction word memory means and adapted to detect positions of operation information and operand specifying information included in an instruction word, and extract operation information and operand specifying information separately, said decoding means being in correspondence to a plurality of instruction formats of instruction words in said main memory; (C) a multiplexer (503, 603) for selecting one of outputs of said plurality of instruction decoding means; (D) control means (506) for controlling said multiplexer; and (E) a memory (303) connected to said multiplexer and having predetermined bit positions for storing operation code information and operand designating information, said system extracting operation information and operand designating information included in an instruction read out of said main memory, arranging said information in said predetermined bit positions in said memory, and implementing processing in accordance with contents of said memory.

Claim 7

A data processing system according to claim 3, wherein said multiplexer control means is adapted to control said control means by executing an instruction in said main memory or an instruction supplied from outside.

Claim 8

A data processing system, in which at least one of instruction words including operation information for specifying an operation to be executed is an instruction which includes at least one operand specifying information for identifying a location of a main memory (102) containing an operand, and said system processes said operand in response to said instruction, said system comprising: (A) instruction memory means (301) for sequentially, in general, searching and storing instruction words entered successively; (B) instruction decoding means (302) connected to said instruction word memory means and adapted to detect locations of operation information and operand specifying information included in an instruction word and extract operation information and operand specifying information separately; (C) a memory (303) having predetermined bit positions for storing operation information and operand specifying information; (D) a first bus (3021) for transferring information which has been extracted and arranged for storing operation information and operand specifying information included in an instruction word read out of said main memory in said predetermined bit positions of said memory; (E) a second bus (6011) for connecting said memory with said main memory; (F) a multiplexer (603) operative to select one of said first bus and said second bus; and (G) a control circuit (604, 606) operative to control said multiplexer, said system implementing process in accordance with information stored in said memory.

Claim 9

A data processing system, in which at least one of instruction words including operation information for specifying an operation to be executed is an instruction which includes at least one operand specifying information for identifying a location of a main memory (102) containing an operand, and said system processes said operand in response to said instruction, said system comprising: (A) instruction memory means (301) for sequentially, in general, searching and storing instruction words entered successively; (B) instruction decoding means (302) connected to said instruction word memory means and adapted to detect locations of operation information and operand specifying information included in an instruction word and extract operation information and operand specifying information separately; (C) a memory (303) having predetermined bit positions for storing operation information and operand specifying information; (D) a first bus (3021) for transferring information which has been extracted and arranged for storing operation information and operand specifying information included in an instruction word read out of said main memory in said predetermined bit positions of said memory; (E) a second bus (6011) for connecting said memory with said main memory; (F) a multiplexer (603) operative to select one of said first bus and said second bus; and (G) a control circuit (604, 606) operative to control said multiplexer, said system implementing process in accordance with information stored in said memory.

Claim 10

A data processing system according to claim 5, wherein said multiplexer control means is adapted to control said control means by executing an instruction in said main memory or an instruction supplied from outside.

Claim 11

A data processing system according to claim 5, wherein said main memory for storing instructions and operands and said data processor are constructed on a single semiconductor substrate.

Claim 12

A data processing system operative to control an operation section (204) thereof by reading out a microinstruction at a relevant address in a microprogram memory (202) in accordance with an instruction word supplied from outside, said system comprising: (A) instruction word memory means (301) for sequentially, in general, searching and storing at least one instruction word in instruction words entered successively from outside; and (B) instruction decoding means (302) connected to said instruction word memory means and adapted to generate addresses of said microprogram memory by decoding said instruction word, said instruction decoding means comprising: code collation means (802) for collating an instruction code with predetermined information to detect the coincidence; code arrangement information memory means - (803) which receives a result from said code collation means and defines arrangement information for changing whole or part of the instruction code; and arranging means (804) connected to said code arrangement information memory means and adapted to arrange the instruction code in accordance with said arrangement information, a result from said arranging means in correspondence to said instruction code being an address of said microprogram memory.

Claim 13

A data processing system operative to control an operation section (204) thereof by reading out a microinstruction at a relevant address in a microprogram memory (202) in accordance with an instruction word supplied from outside, said system comprising: (A) instruction word memory means (301) for sequentially, in general, searching and storing at least one instruction word in instruction words entered successively from outside; and (B) instruction decoding means (302) connected to said instruction word memory means and adapted to generate addresses of said microprogram memory by decoding said instruction word, said instruction decoding means comprising: code collation means (802) for collating an instruction code with predetermined information to detect the coincidence; code arrangement information memory means - (803) which receives a result from said code collation means and defines arrangement information for changing whole or part of the instruction code; and arranging means (804) connected to said code arrangement information memory means and adapted to arrange the instruction code in accordance with said arrangement information, a result from said arranging means in correspondence to said instruction code being an address of said microprogram memory.

Claim 14

A data processing system according to claim 8, wherein at least one of said code collation means and code arrangement information memory means is formed of a programmable logic array (902, 903).

Claim 15

A data processing system according to claim 8, wherein said code collation means is formed of a random access read/write memory constructed of memory cells capable of detecting the coincidence of a memorized value with a value on data lines.

Claim 16

A data processing system for sequentially executing instruction words read out of a main memory (102) or instruction words supplied from outside, said system being provided with instruction word memory means (1500) for sequentially, in general, searching and storing at least one instruction words in instruction words resumed successively from said main memory, said instruction word memory means comprising a memory section for storing an instruction word and a control section for controlling the data read/write operation for said memory section, said instruction word memory means being capable of reading out data in a data length half a data length used in a single write operation.

Claim 17

A data processing system for sequentially executing instruction words read out of a main memory (102) or instruction words supplied from outside, said system being provided with instruction word memory means (1500) for sequentially, in general, searching and storing at least one instruction words in instruction words resumed successively from said main memory, said instruction word memory means comprising a memory section for storing an instruction word and a control section for controlling the data read/write operation for said memory section, said instruction word memory means being capable of reading out data in a data length half a data length used in a single write operation.

Claim 18

A data processing system according to claim 11, wherein said memory control section is formed of a programmable logic array.

Claim 19

A data processing system of the type of multiple register sets system having an additional main memory (102) for storing instructions and operands and adapted to implement data processing in response to said instructions, said system comprising: a. task number specifying means (2105) for specifying a task number which identifies arbitrary one of a plurality of register sets; b. number-of-tasks memory means (2106) for memorizing information capable of identifying said plurality of register sets; c. a random access readlwrite memory (102) which forms part or whole of said main memory and has a capacity larger than a memory capacity necessary for forming register sets in number specified by said number-of-tasks memory means; and d. address generating means (2104) connected with said memory and adapted to produce a physical address of said memory from register specifying information included in an instruction word and said task number, said system being operative to make access to a memory location indicated by a physical address provided by said address generating means upon confirming that the task number specified by said task number specifying means does not exceed a total number of tasks memorized in said number-of-tasks memory means when said instruction is an instruction having access to a register.

Claim 20

A data processing system of the type of multiple register sets system having an additional main memory (102) for storing instructions and operands and adapted to implement data processing in response to said instructions, said system comprising: a. task number specifying means (2105) for specifying a task number which identifies arbitrary one of a plurality of register sets; b. number-of-tasks memory means (2106) for memorizing information capable of identifying said plurality of register sets; c. a random access readlwrite memory (102) which forms part or whole of said main memory and has a capacity larger than a memory capacity necessary for forming register sets in number specified by said number-of-tasks memory means; and d. address generating means (2104) connected with said memory and adapted to produce a physical address of said memory from register specifying information included in an instruction word and said task number, said system being operative to make access to a memory location indicated by a physical address provided by said address generating means upon confirming that the task number specified by said task number specifying means does not exceed a total number of tasks memorized in said number-of-tasks memory means when said instruction is an instruction having access to a register.

Claim 21

A data processing system according to claim 13, wherein said number-of-tasks memory means comprises a memory capable of being addressed by an instruction word, said memory being capable of rewriting through execution of said instruction word.

Claim 22

A data processing system according to claim 13, wherein said task number specifying means comprises a task number specifying register - (2114) which can be accessed by an instruction word and can be rewritten through execution of said instruction, said system implementing task process by revising contents of said task number specifying register by a constant number each time a task switching request occurs.

Claim 23

A data processing system according to claim 13 further comprising addressing means (2125) capable of indicating an arbitrary physical address location of said main memory, said system making access to a predetermined corresponding portion of said memory when a continuous memory range from a first physical address to a second physical address different from said first physical address of said main memory indicated by said address specifying means is accessed.

Claim 24

A data processing system according to claim 13 further comprising detection means (2108) for detecting that a task number specified by said task number specifying means has exceeded a total number of tasks indicated by information stored in said number-of-tasks memory means. A data processing system according to claim 13 wherein said address generating means comprises: a. a first rewritable register (2121, 2122) capable of being specified by an instruction word; and b. identification means (2123, 2124) capable of identifying a series of registers numbered by one register number through another register number which are set in a register set, said first register having contents capable of specifying one of said two register numbers, said system making access to a register with a corresponding register number in a register set indicated by a task number which has been determined irrespective of a current task number when an instruction has specified a register included in said series of registers during execution of a task.

Claim 25

A data processing system according to claim 13, wherein said address generating means comprises: a. a first rewritable register (2121, 2122) capable of being specified by an instruction word; and b. identification means (2123, 2124) capable of identifying a series of registers numbered by one register number through another register number which are set in a register set, said first register having contents capable of specifying one of said two register numbers, said system making access to a register with a corresponding register number in a register set indicated by a task number immediately preceding a current task number when a register included in said series of registers has been accessed by an instruction during execution of a task following at least one task change.

Claim 26

A microprogram control system operative to read out a microinstruction from a memory which stores a plurality of microinstructions in accordance with information held in a memory ad- ' dress register, store said microinstruction in a microinstruction register, and control an operation section basing on contents of said microinstruction register, said system comprising: first means which inhibits renewal of said memory address register upon occurrence of a signal for suspending functions of said system; and second means which generates a specific signal for invalidating a read-out microinstruction so that said operation section performs nothing apparently, whereby said microprogram control system halts its functions apparently without suspension of a basic clock supplied to said memory for storing microinstructions and without halting the read-out operation for said memory.

Claim 27

A microprogram control system operative to read out a microinstruction from a memory which stores a plurality of microinstructions in accordance with information held in a memory ad- ' dress register, store said microinstruction in a microinstruction register, and control an operation section basing on contents of said microinstruction register, said system comprising: first means which inhibits renewal of said memory address register upon occurrence of a signal for suspending functions of said system; and second means which generates a specific signal for invalidating a read-out microinstruction so that said operation section performs nothing apparently, whereby said microprogram control system halts its functions apparently without suspension of a basic clock supplied to said memory for storing microinstructions and without halting the read-out operation for said memory.

Claim 28

A microprogram control system according to claim 20, wherein said first means for inhibiting renewal of said memory address register comprises a NOR gate which receives a basic clock for renewing said memory address register and a signal for halting functions of said microprogram control system.

Claim 29

A microprogram control system according to claim 20, wherein said second means for invalidating a read-out microinstruction so that said operation section performs nothing apparently is operative to inhibit renewal of said microinstruction register and making whole output of said microinstruction register to be a low level invariably.

Claim 30

A microprogram control system according to claim 20, wherein said second means for invalidating a read-out microinstruction so that said operation section performs nothing apparently comprises a logic circuit connected to the output of said microinstruction register, said logic circuit being provided with a function of logical product or logical sum for a signal from said microinstruction register and a signal for halting functions of said microprogram control system so that the input from said microinstruction register is invalidated by the signal for halting functions of said microprogram control system.

Claim 31

A data processing system adapted to control its operation section in such a way of reading out a microinstruction from a microprogram memory addressed by an instruction read out of a main memory or an instruction supplied from outside, decoding said instruction and producing a control signal for said operation section, said system comprising a register control decoder for producing a control signal for controlling read/write operations of registers within said operation section in accordance with a microinstruction, said decoder being formed of an AND-type dynamic programmable logic array, said array having output lines precharged by use of p-channel MOS transistors, said register being controlled for reading and writing by a signal outputted during a precharge period with a first specific level of said signal being defined to be an unselected state for input/output of said register, and with a second specific level of said signal being defined to be selected state for input/output of said register at a time of discharging for only output lines which satisfy a logic of said programmable logic array upon completion of precharge period.

Claim 32

A data processing system adapted to control its operation section in such a way of reading out a microinstruction from a microprogram memory addressed by an instruction read out of a main memory or an instruction supplied from outside, decoding said instruction and producing a control signal for said operation section, said system comprising a register control decoder for producing a control signal for controlling read/write operations of registers within said operation section in accordance with a microinstruction, said decoder being formed of an AND-type dynamic programmable logic array, said array having output lines precharged by use of p-channel MOS transistors, said register being controlled for reading and writing by a signal outputted during a precharge period with a first specific level of said signal being defined to be an unselected state for input/output of said register, and with a second specific level of said signal being defined to be selected state for input/output of said register at a time of discharging for only output lines which satisfy a logic of said programmable logic array upon completion of precharge period.

Claim 33

A data processing system according to claim 24, wherein said programmable logic array has its output lines connected together so as to achieve a logical sum function for the array outputs.