Patent EP0198673A2 successfully refreshed from Google Patents.
EP0198673A2
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EP
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Image memory
Assignee: Fujitsu Ltd
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Filing: 1986-04-10
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Granted: —
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Expires: 2006-04-10
Abstract
Abstract A video random access memory (Video RAM) comprises a plurality of RAM and shift register sets, each RAM (7) being randomly accessed and each shift register (3) being serially accessed, each RAM and corresponding shift register being connected by transfer gates (8) in orderto transfer read/write data. Ther Video RAM further comprises an input/output circuit (4) which is operatively connected to the shift registers and is switched from an input side to an output side, or from an output side to an input side, in response to the direction of data transfer between the RAM and the shift register, and a transfer control circuit (5) for controlling the switching of the input/output circuit and for controlling the direction of data transfer, based on predetermined modes of the input signals.
Inventors
- 👤 Junji Ogawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 03:11
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/10; G11C7/1075
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
122 words
A video random access memory (Video RAM) comprising a plurality of RAM and shift register sets, each RAM (7) being randomly accessed and each shift register (3) being serially accessed, and each RAM and shift register being connected by transfer gates (8). in order to transfer read/write data, characterised by an input/output circuit (4) operatively connected to the shift register and switchable from an input side to an output side or from an output side to an input side in response to the direction of data transfer between the RAM and the shift register, and transfer control means (5,9,16) for controlling the switching of the input/output circuit and for controlling said direction of data transfer based on predetermined modes of input signals.
Claim 2
Dependent Claim
122 words
A video random access memory (Video RAM) comprising a plurality of RAM and shift register sets, each RAM (7) being randomly accessed and each shift register (3) being serially accessed, and each RAM and shift register being connected by transfer gates (8). in order to transfer read/write data, characterised by an input/output circuit (4) operatively connected to the shift register and switchable from an input side to an output side or from an output side to an input side in response to the direction of data transfer between the RAM and the shift register, and transfer control means (5,9,16) for controlling the switching of the input/output circuit and for controlling said direction of data transfer based on predetermined modes of input signals.
Claim 3
Dependent Claim
73 words
A Video RAM as claimed in claim 1, characterised in that the transfer control means comprises a memory (9) for storing a previous transfer state, a transfer command circuit (15) for commanding a transfer signal to the shift register (3) and for controlling ON/OFF switching of the transfer gate (8), and a mode recognition and clock circuit (16) for recognising predetermined modes in order to control the memory and the transfer command circuit.
Claim 4
Dependent Claim
46 words
A Video RAM as claimed in claim 2, characterised in that the mode recognition and clock circuit (16) comprises three clocked D-type latch circuits (L1-L3) for inputting four kinds of commands and one OR gate (OR1) and three AND gate (A1-A3) circuits for outputting read/write signals.
Claim 5
Dependent Claim
29 words
A Video RAM as claimed in claim 2 or claim 3, characterised in that the memory (9) comprises a flip-flop circuit (Q1-Q4) for latching a serial read/write transfer state.
Claim 6
Dependent Claim
24 words
A Video RAM as claimed in claim 4, characterised in that the memory (9) further comprises a monostable multivibrator for switching the input/output mode.
Claim 7
Dependent Claim
39 words
A Video RAM as claimed in any one of claims 2 to 5, characterised in that the transfer command circuit (15) comprises a logic circuit for controlling the transfer gate (8), a word driver (14), and a pointer-decoder (13).
Claim 8
Dependent Claim
23 words
A Video RAM as claimed in any preceding claim, characterised in that the direction of data transfer is determined by four transfer modes.
Claim 9
Dependent Claim
31 words
A Video RAM as claimed in claim 7, characterised in that the four transfer modes comprise an asynchronous mode, a read transfer mode, a write transfer mode, and a non-transfer mode.
Claim 10
Dependent Claim
27 words
A Video RAM as claimed in claim 7 or claim 8, characterised in that each of the transfer modes is constituted by combining the four transfer modes.
Claim 11
Dependent Claim
28 words
A Video RAM as claimed in claim 9, characterised in that each of the transfer modes is detected by the trailing edge of a row address strobe signal.
References Cited (Backward Citations)
No citation records indexed.
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