Semiconductor memory device

Claim 2

A semiconductor device wherein a semiconductor substrate (10) of a first conductivity type is provided with grooves (12) which are formed on said substrate (10) to define a plurality of island layers (14) having side surface regions and top surface regions, and wherein memory cells each of which comprises a capacitor (C) and a transistor (Q) are formed on said substrate (10), characterized in that said capacitor (C) is buried in a groove (12) surrounding one island layer (14) and comprises a capacitor electrode layer (22) insulatively provided over the bottom surface of said groove - (12), and a semiconductor layer (20, 86, 88) of a second conductivity type formed in the side surface region of said groove (12) to face said capacitor electrode layer (12), and that said transistor (Q) comprises a gate electrode layer (28, 80, 82) which is formed in said groove (12) so as to be insulatively stacked over said capacitor electrode layer (22) and which faces the corresponding side surface region of said island layer (14).

Claim 3

The memory device according to claim 1, characterized in that said transistor comprises: a second semiconductor layer (32) of the first conductivity type serving as a drain layer of said transistor and formed on said top surface region of said island layer; and a third semiconductor layer (26, 90) of the second conductivity type being formed on said side surface region of said island layer (14) so as to serve as a channel region of said transistor (Q).

Claim 4

The memory device according to claim 2, characterized in that said second semiconductor layer - (32) is formed to cover said top surface region of said island layer.

Claim 5

The memory device according to claim 3, characterized in that said first semiconductor layer (20) and said gate electrode layer (28) are formed in a square-shaped manner to surround said side surface of said island layer, thereby providing one cell transistor and one cell capacitor in each island layer.

Claim 6

The memory device according to claim 3, characterized in that said first semiconductor layer is divided into two C-shaped layer components (86, 88) which are electrically separated from each other, thereby providing two cell capacitors in each island layer.

Claim 7

The memory device according to claim 5, characterized in that said gate electrode layer is divided outside said island layer into two C-shaped layer components (80, 82) which are electrically insulated from each other, thereby providing two cell transistors (Ql, Q2) in each island layer (14).

Claim 8

A manufacturing method of a semiconductor memory device, characterized in that a plurality of island layers (14) having side surface regions and top surface regions are formed on a semiconductive substrate (10) of a first conductive type which are defined by grooves (12) having bottom surfaces, characterized in that said-method comprises the steps of: forming a capacitor (C) in a groove (12) surrounding an island layer (14), said capacitor (C) comprising a capacitor electrode layer (22) which is insulatively provided over the bottom surface of said groove (12), and a semiconductor capacitor layer - (20, 86, 88) of a second conductivity type formed in the side surface region of said groove (12), said capacitor layer (20,86, 88) being formed in said side surface region of said groove (12) to face said capacitor electrode layer (22); and forming a transistor (Q) in said island layer (14), said transistor (Q) comprising a gate electrode layer (28, 80, 82) formed in said groove (12) so as to be insulatively stacked over said capacitor electrode layer (22), said gate electrode layer (28, 80, 82) facing the corresponding side surface region of said island layer (14).

Claim 9

A manufacturing method of a semiconductor memory device, characterized in that a plurality of island layers (14) having side surface regions and top surface regions are formed on a semiconductive substrate (10) of a first conductive type which are defined by grooves (12) having bottom surfaces, characterized in that said-method comprises the steps of: forming a capacitor (C) in a groove (12) surrounding an island layer (14), said capacitor (C) comprising a capacitor electrode layer (22) which is insulatively provided over the bottom surface of said groove (12), and a semiconductor capacitor layer - (20, 86, 88) of a second conductivity type formed in the side surface region of said groove (12), said capacitor layer (20,86, 88) being formed in said side surface region of said groove (12) to face said capacitor electrode layer (22); and forming a transistor (Q) in said island layer (14), said transistor (Q) comprising a gate electrode layer (28, 80, 82) formed in said groove (12) so as to be insulatively stacked over said capacitor electrode layer (22), said gate electrode layer (28, 80, 82) facing the corresponding side surface region of said island layer (14).

Claim 10

The manufacturing method according to claim 7, characterized in that said capacitor (C) is formed by: implanting an impurity of the second conductivity type in the surface region of said island layer, thereby forming a first semiconductor layer (56) of the second conductivity type corresponding to said semiconductor capacitor layer in the surface region of said island layer to cover at least side surfaces thereof; and providing a first conductive layer (60') corresponding to said capacitor electrode layer in said groove surrounding said island layer to surround side surfaces of substantially a lower half of said island layer, such that substantially an upper half of said island layer is exposed.

Claim 11

The manufacturing method according to claim 8, characterized in that said transistor is formed by: implanting an impurity of the first conductivity type in the exposed upper half of said island layer (14), thereby forming, on the exposed surface of said island layer, a second semiconductor layer (62) of the first conductivity type which serves as a channel region of said transistor; forming a second conductive layer (66') in said groove to surround side surfaces of said second semiconductor layer formed in the surface region of the upper half of said island layer; and implanting an impurity of the second conductivity type in the top surface of said island layer, thereby forming a third semiconductor layer (70) which serves as a drain layer of said transistor to cover the top surface of said island layer.

Claim 12

The manufacturing method according to claim 7, characterized in that the capacitor-forming step comprises the steps of: implanting an impurity of the second conductivity type in the surface region of said island layer, thereby forming a first semiconductor layer of the second conductivity type therein to cover at least said side surfaces of said island layer, said first semiconductor layer being divided into two C-shaped layer components (86, 88) which are electrically separated from each other around said island layer, and said C-shaped layer components - (86, 88) serving as two semiconductor capacitor layers of two neighbouring cell capacitors; and providing a first conductive layer (60') in said groove surrounding said island layer to surround a side surface of substantially a lower half of said island layer, such that substantially an upper half of said island layer is exposed.

Claim 13

The manufacturing method according to claim 10, characterized in that the transistor-forming step comprises the steps of: implanting an impurity of the first conductivity type in the exposed upper half of said island layer, thereby forming a second semiconductor layer - (90) of the first conductivity type in the exposed surface of said island layer; forming a second conductive layer in said groove to surround the side surface of said second semiconductor layer (90) formed in the surface region of the upper half of said island layer such that the top surface of said island layer is exposed, said second conductive layer (90) being devided outside said island layer into two C-shaped layer components (80, 82) serving as two gate electrode layers of two neighbouring cell transistors; providing an insulative layer (84) between said two C-shaped layer components (80, 82); and implanting an impurity of the second conductivity type in the exposed top surface region of said island layer, thereby forming a third semiconductor layer (70) which serves as a common drain layer of said two neighbouring cell transistors (Q1, Q2) to cover said top surface of said island layer.