Patent EP0197758A2 successfully refreshed from Google Patents.
EP0197758A2
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Tone restoring apparatus
Assignee: Panasonic Holdings Corp
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Filing: 1986-04-02
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Granted: —
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Expires: 2006-04-02
Abstract
Abstract In a tone-restoring apparatus, a first and a second hold circuit (4, 5) latch at a period of 2T data signals read from a digital memory (2) in response to a first and a second address supplied to the digital memory (2), and a first and second multiplier circuit multiply the data signals latched in the first and second hold circuit by a monotonously increasing weighting function W,(x) (0 ≤ x ≤ NT, 0 ≤ W 1 (x) ≤ 1) or a monotonously increasing weighting function W 2 (x) (0 ≤ x ≤ NT, 0 ≤ W 2 (x) ≤ 1). An adder circuit (8) adds the output signals from the first and second multiplier circuits to each other.
Inventors
- 👤 Yasutoshi Nakama
- 👤 Masayuki Misaki
- 👤 Seiichi Ishikawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 21:20
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B27/00; G11B27/005; G10; G10L; G10L21/00; G10L21/04; G11B20/00007; G11B2220/00; G11B2220/90
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
224 words
A tone-restoring apparatus comprising: an analog-to-digital converter circuit (1) for converting an input signal to a digital signal by sampling said input signal at a period satisfying a sampling rule, and supplying said digital signal to a digital memory (2) in which said digital signal is stored; a write/read control circuit (3) for producing a write/read control signal to specify a write/read address to said digital memory (2) and to control said digital memory to write and read in response to input address data generated from a write address generator (11) and first and second read address generator circuits (12, 13); first and second hold circuits (4, 5) for latching at a period of 2T signals read from said digital memory (2) in response to first and second read addresses to said digital memory (2); first and second multiplier circuits (6, 7) for multiplying said signals latched in said first and second hold circuits (4, 5) by a monotonously increasing weighting function W 1 (x) (0 < x < NT, 0 < W 1 (x) ≤ 1) or a monotonously decreasing weighting function W 2 (x) an adder circuit 8 for adding the output signals from said first and second multiplier circuits (6, 7); and a digital-to-analog converter circuit (16) for converting the output signal from said adder circuit (8) to an analog signal.
Claim 2
Dependent Claim
224 words
A tone-restoring apparatus comprising: an analog-to-digital converter circuit (1) for converting an input signal to a digital signal by sampling said input signal at a period satisfying a sampling rule, and supplying said digital signal to a digital memory (2) in which said digital signal is stored; a write/read control circuit (3) for producing a write/read control signal to specify a write/read address to said digital memory (2) and to control said digital memory to write and read in response to input address data generated from a write address generator (11) and first and second read address generator circuits (12, 13); first and second hold circuits (4, 5) for latching at a period of 2T signals read from said digital memory (2) in response to first and second read addresses to said digital memory (2); first and second multiplier circuits (6, 7) for multiplying said signals latched in said first and second hold circuits (4, 5) by a monotonously increasing weighting function W 1 (x) (0 < x < NT, 0 < W 1 (x) ≤ 1) or a monotonously decreasing weighting function W 2 (x) an adder circuit 8 for adding the output signals from said first and second multiplier circuits (6, 7); and a digital-to-analog converter circuit (16) for converting the output signal from said adder circuit (8) to an analog signal.
Claim 3
Dependent Claim
238 words
A tone-restoring apparatus according to Claim 1, wherein 2N signals d 0 , d 1 , d 2 , ...., d2N-1 are stored in said digital memory (2) at a period of T from a reference time t=0, the N signals d 0 , d 1 , d 2 , ...., d N-1 are read from said digital memory (2) and held in said first hold circuit (4) at a period of 2T during a time t, 0 < t < 2NT, the N signals d N , d N+1 , d N+2 , ...., d 2N-1 are read from said digital memory (2) and held in said second hold circuit (5) at a period of 2T during NT < t < 3NT, the output signal from said first hold circuit (4) is multiplied by W 1 (t) during the time t, 0 < t < NT and W 2 (t-NT) during the time t, NT < t < 2NT in said first multiplier circuit (6), and the output from said second hold circuit (5) is multiplied by W 2 (t) during the time t, 0 < t < NT and W 1 (t-NT) during the period t, NT < t < 2NT in said second multiplier circuit (7), the multiplying coefficients of said multipliers (6, 7) being controlled by an amplitude control circuit (9), said writing, reading and amplitude control being repeated at a period of 2NT.
Claim 4
Dependent Claim
32 words
A tone-restoring apparatus according to Claim 1, wherein an adaptive delta modulation system is used for the analog-to-digital conversion, and the amplitude control is made by a one-bit adaptive digital-to-analog converter circuit.
Claim 5
Dependent Claim
79 words
A tone-restoring apparatus according to Claim 1, wherein an adaptive delta modulation system is used for the aralog-to-digital conversion, this modulation system using a delta modulator having a compresion-and-expansion circuit that changes the output of an integrator by increasing the quantization step width when a plurality of the delta modulated digital data of one bit, "1" or "0" occur in sequence, and the adaptive quantization step width is determined by a pulse width modulator circuit in the delta modulator.
Claim 6
Dependent Claim
29 words
A tone-restoring apparatus according to Claim 4, wherein said pulse width modulator circuit employs a linear pulse-width modulator circuit for linearly converting the pulse count to a pulse width.
Claim 7
Dependent Claim
29 words
A tone-restoring apparatus according to Claim 4, wherein said pulse width modulator circuit employs a nonlinear pulse-width modulator circuit for nonlinearly converting the pulse count to a pulse width.
Claim 8
Dependent Claim
25 words
A tone-restoring apparatus according to Claim 4, wherein the multiplier and multiplicand in said first and second multiplier circuits are both a pulse-width modulated signal.
Claim 9
Dependent Claim
155 words
An adaptive delta modem according to Claim 3, wherein said adaptive delta modulator comprises: a comparator (30) for comparing an analog input signal with a fed-back signal; a sampling circuit (31) for producing a digital signal of one bit; a quantization step width adaptive logic circuit; an m-bit up/down counter (33); a decoder (34) for decoding an m-bit output to n bits; a pulse width modulator circuit (35) for converting an n-bit output from said decoder to a pulse width; a polarity switching circuit (36) for switching the output from said pulse-width modulating circuit between positive and negative polarities; and an integrator circuit (37) for integrating the output from said polarity switching circuit, thereby converting it to an analog signal, and producing said fed-back signal, said adaptive delta demodulator comprises the same components as those of said adaptive delta modulator except said comparator, and a low pass filter at the output of said integrator circuit.
Claim 10
Dependent Claim
40 words
An adaptive delta modem according to Claim 8, wherein a pulse-width modulator circuit for converting the output from said m-bit up/down counter to a pulse width is used instead of said decoder for converting an m-bit output to n bits.
References Cited (Backward Citations)
No citation records indexed.
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