Patent EP0196771A2 successfully refreshed from Google Patents.
EP0196771A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Improved programmable logic device
Assignee: Lattice Semiconductor Corp
•
Filing: 1986-02-25
•
Granted: —
•
Expires: 2006-02-25
Abstract
Abstract An improved programmable logic device (PLD) is disclosed which employs electrically erasable memory cells which can be programmed and erased at high speed. The PLD memory cells comprise floating gate transistors as the storage elements, which are programmed and erased by Fowler-Nordheim tunneling. The PLD includes a serial register latch (SRL) 30 which is coupled to the product terms of the PLD array 10. Input programming data for a selected row of the array is serially entered into the SRL <sub>1</sub>0, and during a programming cycle the SRL data is employed to simultaneously program the storage elements of the selected row to either the enhancement mode or the depletion mode. The data programmed into the array 10 may be verified at high speed. The status of each of the cells in the selected row can be sensed using the normal sense amplifiers and loaded into the SRL 30 in parallel, and thereafter serially shifted out of the PLD for external verification. The PLD output logic and sense amplifiers can be functionally validated independent of the data in the array. Test data such as apparent array patterns are serially loaded into the SRL, and thereafter forced onto the normal sense amplifier inputs, propagated through the output logic and read out of the device output pin.
Inventors
- 👤 John E. Turner
- 👤 David L. Rutledge
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 23:15
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516; H03K19/177; H03K19/17704; H03K19/17748; H03K19/17758; H03K19/1776; H03K19/17764; H03K19/1778
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
115 words
In a programmable logic device comprising a plurality of input lines, a plurality of product terms, a matrix of programmable cells each selectively coupling respective ones of -said input lines to respective ones of said product terms, and output logic circuits coupling said product terms to device terminals, the improvement chracterized in that said programmable cells comprise electrically erasable floating gate transistors employing Fowler-Nordheim tunneling to achieve charge transfer between the floating gate and the transistor drain so that the transistor may be operated in either the enhancement mode or the depletion mode, whereby the transistor is either conductive or nonconductive when an interrogation signal is applied to the gate of the floating gate transistor.
Claim 2
Dependent Claim
115 words
In a programmable logic device comprising a plurality of input lines, a plurality of product terms, a matrix of programmable cells each selectively coupling respective ones of -said input lines to respective ones of said product terms, and output logic circuits coupling said product terms to device terminals, the improvement chracterized in that said programmable cells comprise electrically erasable floating gate transistors employing Fowler-Nordheim tunneling to achieve charge transfer between the floating gate and the transistor drain so that the transistor may be operated in either the enhancement mode or the depletion mode, whereby the transistor is either conductive or nonconductive when an interrogation signal is applied to the gate of the floating gate transistor.
Claim 3
Dependent Claim
30 words
2- The improvement of Claim 1 further characterized in that wherein said programmable cells further comprise a cell select transistor whose state is controlled by a respective input line signal.
Claim 4
Dependent Claim
27 words
The improvement of Claim 2 further characterized by means for programming the floating gate transistors comprising said cells to either the enhancement mode or the depletion mode.
Claim 5
Dependent Claim
28 words
The improvement of Claim 3 further characterized in that said programming means is adapted to program in parallel each of the cells coupled to a selected input line.
Claim 6
Dependent Claim
78 words
The improvement of Claim 4 further characterized in that said programming means comprises serial shift register means comprising a plurality of serially-connected stages coupled to corresponding product terms, means for loading the stages of said shift register means with data corresponding to the state to which the cell is to be pro--grammed, and means for applying programming voltages to said cells in dependence on the state of said data in the respective stages of the shift register means.
Claim 7
Dependent Claim
32 words
The invention of Claim 5 further characterized in that said programming means comprises bulk erasing means for simultaneously programming each of the floating gate transistors comprising the cells to the enhancement mode.
Claim 8
Dependent Claim
58 words
The invention of Claim 6 further characterized in that said bulk erasing means comprises means for applying high programming potential to the gates of said floating gate transistor means, means for driving each of said select transistors to the conductive state, and means for grounding the respective drains of said floating gate transistors during a bulk erase cycle.
Claim 9
Dependent Claim
60 words
In a programmable logic device comprising a matrix of rows and columns of programmable cells, an improved programming and verification circuit characterized by: programming means for simultaneously programming the cells of a selected row of said matrix to predetermined states; and verification means for sensing in parallel the respective states of the cells comprising a selected row in said array.
Claim 10
Dependent Claim
60 words
In a programmable logic device comprising a matrix of rows and columns of programmable cells, an improved programming and verification circuit characterized by: programming means for simultaneously programming the cells of a selected row of said matrix to predetermined states; and verification means for sensing in parallel the respective states of the cells comprising a selected row in said array.
Claim 11
Dependent Claim
51 words
The invention of Claim 8 further characterized in that the programming means comprises: serial shift register means comprising a plurality of serialiy- connected stages; means for serially shifting into said shift register programming data representative of the state to which the respective cells of a selected column are to be programmed.
Claim 12
Dependent Claim
38 words
The invention of Claim 9 further characterized in that said programming means further comprises coupling means for selectivefy coupling the stages of said shift register to rows of said cells of said matrix during a device programming cycle.
Claim 13
Dependent Claim
42 words
The invention of Claim 9 further characterized in that said verification means comprises said shift register means and loading means for loading data indicative of the status of the cells of a selected row into the corresponding stages of said shift register.
Claim 14
Dependent Claim
51 words
1 2. The invention of Claim 8 further characterized in that said cells of said matrix each comprise first and second transistor means, said first transistor means adapted to select the cell for programming in dependence upon row address selection signals, and said second transistor adapted to store the programmed information.
Claim 15
Dependent Claim
43 words
The invention of Claim 8 further characterized in that said programmable logic device further comprises output circuits coupling the columns of said matrix to device output ports, and wherein said verification means further comprises means for verifying the operation of said output circuitry.
Claim 16
Dependent Claim
28 words
The invention of Claim 13 further characterized in that said output verification means comprises means for loading an apparent array pattern of said matrix into said output circuitry.
Claim 17
Dependent Claim
79 words
The invention of Claim 14 further characterized in that said output circuitry comprises sense amplifiers for sensing the state of respective ones of the cells in selected rows of said matrix, said verification means comprises a serial shift register means comprising a plurality of series-connected stages, one each coupled to a respective one of said sense amplifiers, and wherein said verification means comprises means for forcing the contents of said stages of said shift register onto said sense amplifiers.
Claim 18
Dependent Claim
93 words
An improved programmable logic device adapted for high speed programming and verification of a matrix of programmable cells selectively coupling input lines to respective product terms, characterized by: output circuitry comprising a plurality of sense amplifiers, one each coupled to a respective product term, and output logic devices coupled to the device output ports; programming means arranged to program simultaneously the cells coupled to one input line in accordance with a predetermined programming data pattern; and cell. verification means adapted to verify the programmed states of the cells coupled to selected input lines.
Claim 19
Dependent Claim
93 words
An improved programmable logic device adapted for high speed programming and verification of a matrix of programmable cells selectively coupling input lines to respective product terms, characterized by: output circuitry comprising a plurality of sense amplifiers, one each coupled to a respective product term, and output logic devices coupled to the device output ports; programming means arranged to program simultaneously the cells coupled to one input line in accordance with a predetermined programming data pattern; and cell. verification means adapted to verify the programmed states of the cells coupled to selected input lines.
Claim 20
Dependent Claim
66 words
The programmable logic device of Claim 1 6 further characterized in that said programming means includes a serial shift register latch (SRL) means comprising a plurality of series-connected stages, and wherein each of said stages is selectively coupled to a corresponding one of said product terms, whereby programming data may be serially input into said SRL means via a serial input data port of the device.
Claim 21
Dependent Claim
69 words
The programmable logic device of Claim 17 further characterized by a serial data output port, and in that the verification means comprises said SRL means, means for loading data representative of the state of respective cells of a selected row of said matrix into corresponding stages of said SRL, and means for thereafter serially shifting the contents of said SRL out of the serial data port of said device.
Claim 22
Dependent Claim
50 words
The programmable logic device of Claim 16 further comprised by output circuitry verification means, comprising means for inputting an apparent array pattern into the output circuitry coupled to a selected product term of said matrix, whereby the resulting device output bit pattern may be compared against an expected bit pattern.
Claim 23
Dependent Claim
114 words
An improved programmable logic device a plurality of input lines, a plurality of product term lines, and an array of programmable switch elements, each coupled to predetermined ones of said input lines and said product term lines and arranged to selectively couple said input line to said product term in dependence on the respective switch state, characterized by: a plurality of sensing means, one each coupled to a respective one of said product terms and adapted to sense the state of said product term; output logic circuitry adapted to couple said sense amplifier outputs to device terminals; and verification means adapted to verify the operation of said sensing means and said output logic means.
Claim 24
Dependent Claim
114 words
An improved programmable logic device a plurality of input lines, a plurality of product term lines, and an array of programmable switch elements, each coupled to predetermined ones of said input lines and said product term lines and arranged to selectively couple said input line to said product term in dependence on the respective switch state, characterized by: a plurality of sensing means, one each coupled to a respective one of said product terms and adapted to sense the state of said product term; output logic circuitry adapted to couple said sense amplifier outputs to device terminals; and verification means adapted to verify the operation of said sensing means and said output logic means.
Claim 25
Dependent Claim
51 words
The programmable logic device of Claim 20 further characterized in that said verification means comprises means for forcing an apparent array bit pattern onto the inputs of said sensing means, whereby said bit pattern is propagated through said sense amplifiers and said output logic circuitry in dependence on their operational state.
Claim 26
Dependent Claim
37 words
The programmable logic device of Claim 20 further characterized in that said verification means is adapted to verify the operation of said sense amplifiers and said output logic means without requiring said switch elements to be reprogrammed.
Claim 27
Dependent Claim
56 words
The programmable logic device of Claim 22 further characterized in that said verification means comprises: serial shift register means comprising a plurality of serially-connected stages, each selectively coupled to corresponding ones of said sensing means in response to control signals; and means for loading said apparent bit pattern into the stages of said shift register means.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.