Semiconductor memory

Claim 2

A semiconductor memory of a redundant design having a spare decoder in addition to a regular decoder

Claim 3

(21), characterized in that: a plurality of charging means (14 and 20) are provided in said spare decoder.

Claim 4

(21), characterized in that: a plurality of charging means (14 and 20) are provided in said spare decoder.

Claim 5

A semiconductor memory in accordance with claim 1, comprising: a memory cell array in which memory cells (MC) are regularly arrayed and an arbitrary memory cell can be specified by a column address and a row address, said spare decoder being located outside said memory cell array, whereby a parasitic resistor (19) exists unavoidably between said spare decoder and said memory cell array, and said charging means being provided on both sides of said parasitic resistor.

Claim 6

A semiconductor memory in accordance with claim 2, wherein said spare decoder is a spare column decoder for decoding said column address of said memory cell array.

Claim 7

A semiconductor memory in accordance with claim 2, wherein said spare decoder is a spare row decoder for decoding said row address of said memory cell array.

Claim 8

S. A semiconductor memory of a redundant design comprising: a memory cell array in which a plurality of memory cells (MC) are regularly arrayed along the word lines (WL and WL) and the bit lines (BL and BL) perpendicular to said word lines and an arbitrary memory cell can be specified by the combination of a column address and a row address, reading means (1) for selecting one of said word lines by said row address to read out onto said bit lines, an information charge of the memory cells connected to said selected word line, sense amplifiers (SE) provided for each of said bit lines for amplifying the information charge read out onto said each bit line, means (21, 10, 11, I/O, I/O and 12) for selecting one of said bit lines by said column address to provide to the exterior the information charge amplified by said sense amplifier connected to said selected bit line, and a spare column decoder for selecting a spare bit line when a column address corresponding to a defective bit line is applied, said semiconductor memory being characterized in that a plurality of charging means .(14 and 20) are provided in said spare column decoder.

Claim 9

S. A semiconductor memory of a redundant design comprising: a memory cell array in which a plurality of memory cells (MC) are regularly arrayed along the word lines (WL and WL) and the bit lines (BL and BL) perpendicular to said word lines and an arbitrary memory cell can be specified by the combination of a column address and a row address, reading means (1) for selecting one of said word lines by said row address to read out onto said bit lines, an information charge of the memory cells connected to said selected word line, sense amplifiers (SE) provided for each of said bit lines for amplifying the information charge read out onto said each bit line, means (21, 10, 11, I/O, I/O and 12) for selecting one of said bit lines by said column address to provide to the exterior the information charge amplified by said sense amplifier connected to said selected bit line, and a spare column decoder for selecting a spare bit line when a column address corresponding to a defective bit line is applied, said semiconductor memory being characterized in that a plurality of charging means .(14 and 20) are provided in said spare column decoder.

Claim 10

A semiconductor memory in accordance with claim 5, wherein a parasitic resistor (19) exists unavoidably between said spare column decoder and said memory cell array, and said charging means are provided on both sides of said parasitic resistor.

Claim 11

An address decoder (Fi g. 1) for a semiconductor memory (Fig. 2) comprising a plurality of charging modes (N, N 2 ) coupled to each other by an impedance (19) and charging means (14, 20) for applying charge to said charging modes in response to a clock signal characterised in that said charging means (14, 20) comprises a plurality of charging means individually connected to respective ones of said modes.

Claim 12

An address decoder (Fi g. 1) for a semiconductor memory (Fig. 2) comprising a plurality of charging modes (N, N 2 ) coupled to each other by an impedance (19) and charging means (14, 20) for applying charge to said charging modes in response to a clock signal characterised in that said charging means (14, 20) comprises a plurality of charging means individually connected to respective ones of said modes.

Claim 13

An address decoder as claimed in Claim 7, which is a supplementary decoder for a semiconductor memory.