Patent EP0194462A2 successfully refreshed from Google Patents.
EP0194462A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
System bus means for inter-processor communication
Assignee: LG Electronics Inc
•
Filing: 1986-02-13
•
Granted: —
•
Expires: 2006-02-13
Abstract
Abstract A system bus structure and operation for interprocessor communication in an information processing system (102) incorporating a plurality of processing elements (108, 110, 112, 114, 116), each of which may be capable of independently executing certain information processing or handling operations. The system bus structure (104, 106) comprises an access control bus (106) for conducting a bus access signal indicating the occurrence of an interprocessor communication and a communications bus (104) which includes a first bus for conducting signals indicating that the inter- processor communication is a specifia one of a first class of communications or is a member of a second class of communications and second bus for communicating the information content of the communication. The first class of communications includes memory related communications. The second class of communications includes non-memory related communications. The access control bus (106) comprises a loop, with the processor elements connected in series along the access control bus means loop, and the processor elements are connected in parallel to the communications bus.
Inventors
- 👤 David L. Whipple
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 18:43
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217; G06F13/14; G06F13/36; G06F13/368; G06F13/37; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F15/173; G06F15/17337
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
97 words
1) In an information processing system (102) including a plurality of processor elements (108, 110, 112, 114, 116), system bus means (104, 106) for interprocessor communication, comprising: access control bus means (106) for conducting a bus access signal indicating the occurrence of an interprocessor communication, and communications bus means (104), including first bus means (202) for conducting signals indicating that the interprocessor communication is a specific one of a first class of communications or is a member of a second class of communications, and second bus means (204, 206) for communicating the information content of the communication.
Claim 2
Dependent Claim
97 words
1) In an information processing system (102) including a plurality of processor elements (108, 110, 112, 114, 116), system bus means (104, 106) for interprocessor communication, comprising: access control bus means (106) for conducting a bus access signal indicating the occurrence of an interprocessor communication, and communications bus means (104), including first bus means (202) for conducting signals indicating that the interprocessor communication is a specific one of a first class of communications or is a member of a second class of communications, and second bus means (204, 206) for communicating the information content of the communication.
Claim 3
Dependent Claim
100 words
2) The system bus means of claim 1, wherein: the first class of communications includes memory related communications, and the information content of a communication of the first class includes a source or destination memory address field (214), and if a destination address, a data field (see 206) containing information to be communicated, and the second class of communications includes non-memory related communications, and the information content of a communication of the second class includes a first field (214) indicating the destination element, a second field (216) indicating the type of communication, and a third field (218) containing a message.
Claim 4
Dependent Claim
31 words
3) The system bus means of claim 2, wherein the information content of a communication of the second class further comprises: a data field (see 206) containing information to be communicated.
Claim 5
Dependent Claim
58 words
4) The system bus means of claim 2, wherein the second bus means comprises: address bus means (204) for communicating the address fields of the first class of communications and the first, second and third fields of the second class of communications, and data bus means (206) for communicating the data fields of the first class of communications.
Claim 6
Dependent Claim
113 words
5) The system bus means of claim 1, wherein: the access control bus means (106) comprises a loop with the processor elements (108, 110, 112, 114, l16) connected in a series along the access control bus means loop, and the processor elements are connected in parallel to the communications bus means, and wherein the bus access signal is conducted through the access control bus loop to each processor element in turn along the access control bus loop, so that the relative priorities of access of the processor elements to the communications bus means rotate around the access control bus loop as the bus access signal is propagated around the access control bus loop.
Claim 7
Dependent Claim
162 words
6) In an information processing system including a plurality of processor elements (108, 110, 112, 114, 116) and system bus means (104, 106) for interprocessor communication, the system bus means including access control bus means (106) and communications bus means (104), the communications bus means including first bus means (202) for conducting signals indicating the type of an interprocessor communication and second bus means (204, 206) for communicating the information content of the communication, bus interface means included in a processor element for transmitting and receiving interprocessor communications, comprising: bus access means (302, 304,'305) connected to the access control bus means for asserting or receiving a bus access signal indicating the occurrence of an interprocessor communication, communication type means (308, 312) connected to the first bus means for asserting or receiving signals indicating the type of interprocessor communication to be performed, and information means (308, 314) connected to the second bus means for transmitting or receiving the information content of the communication.
Claim 8
Dependent Claim
162 words
6) In an information processing system including a plurality of processor elements (108, 110, 112, 114, 116) and system bus means (104, 106) for interprocessor communication, the system bus means including access control bus means (106) and communications bus means (104), the communications bus means including first bus means (202) for conducting signals indicating the type of an interprocessor communication and second bus means (204, 206) for communicating the information content of the communication, bus interface means included in a processor element for transmitting and receiving interprocessor communications, comprising: bus access means (302, 304,'305) connected to the access control bus means for asserting or receiving a bus access signal indicating the occurrence of an interprocessor communication, communication type means (308, 312) connected to the first bus means for asserting or receiving signals indicating the type of interprocessor communication to be performed, and information means (308, 314) connected to the second bus means for transmitting or receiving the information content of the communication.
Claim 9
Dependent Claim
38 words
7) The bus interface means of claim 6, wherein: the communication type signals indicate whether the interprocessor communication is a specific one of a first class of communications or is a member of a second class of communications.
Claim 10
Dependent Claim
100 words
8) The bus interface means of claim 7, wherein: the first class of communications includes memory related communications, and the information content of a communication of the first class includes a source or destination memory address field (214), and if a destination address, a data field (see 206) containing information to be communicated, and the second class of communications includes non-memory related communications, and the information content of a communication of the second class includes a first field (214) indicating the destination element, a second field (216) indicating the type of communication, and a third field (218) containing a message.
Claim 11
Dependent Claim
31 words
9) The bus interface means of claim 8, wherein the information content of a communication of the second class further comprises: a data field (see 206) containing information to be communicated.
Claim 12
Dependent Claim
58 words
10) The bus interface means of claim 8, wherein the second bus means comprises: address bus means (204) for communicating the address fields of the first class of communications and the first, second the third fields of the second class of communications, and data bus means (206) for communicating the data fields of the first class of communications.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.