Semiconductor integreated circuit device and method of manufacturing the same

Claim 1

A semiconductor device having a bipolar transistor comprising: a first semiconductor region (29) of a first conductivity type constituting a base region; a second semiconductor region (42) of a second conductivity type formed in a surface layer of said first semiconductor region; and a polycide layer (34) formed of a laminated layer of a polysilicon layer doped with an impurity of the second conductivity type and a metal silicide layer, said polycide layer being in contact with said second semiconductor region to form said second semiconductor region by using said polycide layer as a diffusion source.

Claim 17

A method of manufacturing a semiconductor device, comprising the steps of: selectively forming a field insulation layer on a semiconductor layer of a first conductivity type so as to isolate said layer into a plurality of first semiconductor regions; doping an impurity of a second conductivity type so as to form a base region of the second conductivity type in at least one of said first semiconductor regions; forming one of a polycide layer formed by laminating a polysilicon layer containing an impurity of the first conductivity type with a metal silicide layer, a laminated layer of a polysilicon layer and a refractory metal layer and a metal silicide layer on said base region so as to be in contact with part of said base region and have one end extending over said field insulation layer; and diffusing an impurity of the first conductivity type one of said polycide layer, said laminated layer and said metal silicide layer as a diffusion source into said base region so as to form a second semiconductor region of the first conductivity type.

Claim 18

A method of manufacturing a semiconductor device, comprising the steps of: selectively forming a field insulation layer on a semiconductor layer of a first conductivity type so as to isolate said layer into a plurality of first semiconductor regions; doping an impurity of a second conductivity type so as to form a base region of the second conductivity type in at least one of said first semiconductor regions; forming one of a polycide layer formed by laminating a polysilicon layer containing an impurity of the first conductivity type with a metal silicide layer, a laminated layer of a polysilicon layer and a refractory metal layer and a metal silicide layer on said base region so as to be in contact with part of said base region and have one end extending over said field insulation layer; and diffusing an impurity of the first conductivity type one of said polycide layer, said laminated layer and said metal silicide layer as a diffusion source into said base region so as to form a second semiconductor region of the first conductivity type.

Claim 26

A method of manufacturing a semiconductor device, comprising the steps of: preparing a first semiconductor region of a first conductivity type; forming second and third semiconductor regions of a second conductivity type at a given distance from each other in a surface layer of said first semiconductor region; forming a gate electrode insulatively disposed over a portion between said second and third semiconductor regions and comprising one of a polycide layer formed of a polysilicon layer and a metal silicioe layer laminated on said polysilicon layer, a laminated layer of a polysilicon layer and a refractory metal layer, and a metal silicide layer, said second and third regions ana said gate electrode constitute a metal oxide semiconductor transistor; forming a base region of a second conductivity type formed in a region of the first conductivity type to be spaced apart from said metal oxide semiconductor transistor; forming one of a polycide layer formed of a polysilicon layer containing an impurity of the secono conductivity type and a metal silicide layer laminateo on said polysilicon layer, a laminated layer of a polysilicon layer and a refractory metal layer, and a metal silicide layer, on a surface layer of said base region; and forming a fourth semiconductor region of the secono conductivity type in said base region, using saio polycide layer as a diffusion source.

Claim 27

A method of manufacturing a semiconductor device, comprising the steps of: preparing a first semiconductor region of a first conductivity type; forming second and third semiconductor regions of a second conductivity type at a given distance from each other in a surface layer of said first semiconductor region; forming a gate electrode insulatively disposed over a portion between said second and third semiconductor regions and comprising one of a polycide layer formed of a polysilicon layer and a metal silicioe layer laminated on said polysilicon layer, a laminated layer of a polysilicon layer and a refractory metal layer, and a metal silicide layer, said second and third regions ana said gate electrode constitute a metal oxide semiconductor transistor; forming a base region of a second conductivity type formed in a region of the first conductivity type to be spaced apart from said metal oxide semiconductor transistor; forming one of a polycide layer formed of a polysilicon layer containing an impurity of the secono conductivity type and a metal silicide layer laminateo on said polysilicon layer, a laminated layer of a polysilicon layer and a refractory metal layer, and a metal silicide layer, on a surface layer of said base region; and forming a fourth semiconductor region of the secono conductivity type in said base region, using saio polycide layer as a diffusion source.

Claim 28

A method of manufacturing a semiconductor device, comprising the steps of: selectively forming, in a surface layer of a semiconductor substrate of a first conductivity type, a plurality of high concentration buried layers having a second conductivity type, and growing an epitaxial semiconductor layer of the first conductivity type on an entire surface of said substrate; forming well regions of the second conductivity type which extend from a surface of said epitaxial semiconductor layer to said high concentration buried layers; selectively forming a field insulating film on the surface of said epitaxial semiconductor layer so as to form first conductivity type element regions and second conductivity type element regions surrounded by said field insulating film; forming a thin insulating film on surfaces of said element regions; selectively doping one of said second conductivity type element regions with a first conductivity type impurity so as to form a first conductivity type active base region of a bipolar transistor; forming gate electrodes of MOS transistors interposed with said insulating film on said first conductivity type element regions and remaining ones of said second conductivity type element regions in which said active base region is not formed, said gate electrodes each comprising one of a polycide layer formed of a polysilicon layer and a metal silicide layer laminated on said polysilicon layer, a laminated layer formed of a polysilicon layer and a refractory metal layer laminated on said polysilicon layer, and a metal silicide layer which is doped with an impurity to have a low resistance; forming a second conductivity type emitter region in said first conductivity type active base region; selectively doping a second conductivity type impurity so as to simultaneously form a second conductivity type collector contact region of said bipolar transistor, and second conductivity type source and drain regions of said MOS transistors in said first conductivity source and drain regions being self-aligned with said gate electrodes of said MOS transistors; and selectively doping a first conductivity type impurity so as to form an external base region of the first conductivity type in said first conductivity type base region and first conductivity type source and drain regions of said MOS transistors in said remaining ones of said second conductivity type element regions, said first conductivity type source and drain regions being self-aligned with said gate electrodes of said MOS transistors.

Claim 29

A method of manufacturing a semiconductor device, comprising the steps of: selectively forming, in a surface layer of a semiconductor substrate of a first conductivity type, a plurality of high concentration buried layers having a second conductivity type, and growing an epitaxial semiconductor layer of the first conductivity type on an entire surface of said substrate; forming well regions of the second conductivity type which extend from a surface of said epitaxial semiconductor layer to said high concentration buried layers; selectively forming a field insulating film on the surface of said epitaxial semiconductor layer so as to form first conductivity type element regions and second conductivity type element regions surrounded by said field insulating film; forming a thin insulating film on surfaces of said element regions; selectively doping one of said second conductivity type element regions with a first conductivity type impurity so as to form a first conductivity type active base region of a bipolar transistor; forming gate electrodes of MOS transistors interposed with said insulating film on said first conductivity type element regions and remaining ones of said second conductivity type element regions in which said active base region is not formed, said gate electrodes each comprising one of a polycide layer formed of a polysilicon layer and a metal silicide layer laminated on said polysilicon layer, a laminated layer formed of a polysilicon layer and a refractory metal layer laminated on said polysilicon layer, and a metal silicide layer which is doped with an impurity to have a low resistance; forming a second conductivity type emitter region in said first conductivity type active base region; selectively doping a second conductivity type impurity so as to simultaneously form a second conductivity type collector contact region of said bipolar transistor, and second conductivity type source and drain regions of said MOS transistors in said first conductivity source and drain regions being self-aligned with said gate electrodes of said MOS transistors; and selectively doping a first conductivity type impurity so as to form an external base region of the first conductivity type in said first conductivity type base region and first conductivity type source and drain regions of said MOS transistors in said remaining ones of said second conductivity type element regions, said first conductivity type source and drain regions being self-aligned with said gate electrodes of said MOS transistors.