Patent EP0192578A2 successfully refreshed from Google Patents.
EP0192578A2
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EP
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A multiple bus system including a microprocessor having separate instruction and data interfaces and caches
Assignee: Intergraph Corp
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Filing: 1986-02-21
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Granted: —
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Expires: 2006-02-21
Abstract
Abstract A microprocessor system architecture is disclosed having a high-speed system bus for coupling system elements coupled thereto for high-speed communications thereamong, and having a dual bus microprocessor having separate ultra-high speed instruction and data cache interfaces coupled to independently operable instruction and data caches, respectively. The caches are coupled to the system bus as well as to the microprocessor. A primary main memory is coupled to the system bus for selectively storing and outputting digital information. The instruction and data caches are coupled to the primary memory via the system bus for independently and selectively managing and accessing the primary memory for selectively storing and outputting digital information to respective mapped addressable very high-speed cache memory. The system bus provides a high-speed bus coupled to the primary memory, instruction cache, and data cache, and other system elements, for communicating the information therebetween at a high rate. The microprocessor is coupled via separate and independent very high-speed instruction and data buses to each of the instruction cache and data cache, respectively, for processing data received from the data cache responsive to instructions received from the instruction cache. The instruction bus and data bus are exclusive and independent of one another. This provides for very high speed instruction transfer from the instruction cache to the microprocessor via the instruction bus and allows for simultaneous very high-speed transfer of data between the data cache and the microprocessor via the data bus. The data cache and instruction cache each have separate dedicated system bus interfaces for coupling to the main memory and to other peripheral devices which are coupled to the system bus. Numerous other system elements can also be coupled to the system bus, including an interrupt controller, an I/O processor, a bus arbiter, an array processor, and other peripheral controller devices.
Inventors
- 👤 Howard Gene Sachs
- 👤 Walter H. Hollingsworth
- 👤 James Youngsae Cho
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 12:19
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0848
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
143 words
A processing system eomprising: (a) main memory for selectively storing and outputting digital information from an addressable high speed read-write memory; (b) instruction cache means, coupled to said main memory, for managing the selective access to the main memory for selectively storing and outputting at very high speed digital information data from an addressable very high speed instruction cache read-write memory; (c) data cache means, coupled to said main memory, for managing the selective access to the main memory for selectively storing and outputting at very high speed digital information data from an addressable very high speed read-write memory; and (d) microprocessor processing means, independently coupled to each of said instruction cache means and data cache means, for processing data received from said data cache means responsive to decoding and executing a respective one of said instructions received from said instruction cache means.
Claim 2
Dependent Claim
143 words
A processing system eomprising: (a) main memory for selectively storing and outputting digital information from an addressable high speed read-write memory; (b) instruction cache means, coupled to said main memory, for managing the selective access to the main memory for selectively storing and outputting at very high speed digital information data from an addressable very high speed instruction cache read-write memory; (c) data cache means, coupled to said main memory, for managing the selective access to the main memory for selectively storing and outputting at very high speed digital information data from an addressable very high speed read-write memory; and (d) microprocessor processing means, independently coupled to each of said instruction cache means and data cache means, for processing data received from said data cache means responsive to decoding and executing a respective one of said instructions received from said instruction cache means.
Claim 3
Dependent Claim
132 words
The system as in Claim 1, wherein said processing means is further comprised of means for outputting a cache advance signal; wherein said instruction cache means is further comprised of a program counter selectively incre- mentable responsive to said cache advance signal, for addressing said instruction cache memory; wherein said data cache means is further comprised of an address register for addressing said data cache memory; said system further characterized in that said instruction cache program counter is loaded with an address output from said processing means, said instruction cache means providing an instruction output from the associated addressed location, and wherein thereafter, said instruction cache program counter is incremented responsive to said cache advance signal, such that repetitive instructions are output independent of any further address output from said processing means.
Claim 4
Dependent Claim
24 words
The system as in Claim 2 wherein said repetitive instruction output continues without further processing means intervention until a context switch or branch occurs.
Claim 5
Dependent Claim
61 words
The system as in Claim 2 wherein each transfer of data between said data cache means and said processor means is comprised of: said processor means outputting an address associated with the data to be transferred, then said data cache address register loading said output address, and then transfer of said data between said data cache means and said processor means.
Claim 6
Dependent Claim
19 words
The system as in Claim 4 wherein each said data transfer is comprised of a plurality of data words.
Claim 7
Dependent Claim
23 words
The system as in Claim 2 wherein said instruction cache program counter is loaded with an address only during context switches and branches.
Claim 8
Dependent Claim
62 words
The system as in Claim 1 wherein said processing means is further comprised of: instruction interface means for controlling communications with an external instruction cache and for coupling of instructions from said instruction cache to the processing means; and data interface means for controlling communications with an external data cache and for bidirectionally communicating data between said data cache and the microprocessor.
Claim 9
Dependent Claim
67 words
The system as in Claim 1: wherein said processing means provides a virtual address output which is associatively mapped to a physical main memory address; and wherein each of said instruction and data cache means are each further comprised of respective memory management means responsive to a separate respective one of said virtual address outputs for selectively providing a respective output of the associated mapped digital information.
Claim 10
Dependent Claim
47 words
The system as in Claim 8 wherein said data cache memory management means provides for said output of the associated mapped digital information from the data cache memory when present therein, and otherwise provides for said output of the associated mapped digital information from said main memory.
Claim 11
Dependent Claim
232 words
A microprocessor based computer system comprising: primary memory means for selectively storing and outputting digital information from an addressable high speed memory; a high speed systems. bus coupled to the primary memory means for communicating digital information between means coupled to said system bus; instruction cache means, coupled to said system bus, for managing the selective retrieval of instructions from said primary memory, and for selectively storing said instructions therefrom in a mapped addressable very high speed memory for providing selective very high speed output of said instructions from said high speed memory; data cache means, coupled to said system bus, for managing the selective storage and retrieval of data to and from said primary memory, and for selectively storing and outputting said data at very high speed to and from a mapped addressable very high speed memory; a very high speed instruction bus coupled to said instruction cache means for communicating said very high speed instruction output from said instruction cache along said instruction bus; a very high speed data bus coupled to said said data cache means for communicating data at said very high speed to and from said data cache means along said data bus; and microprocessor processing means, independently coupled to each of said instruction bus and said data bus, for selectively processing data received from said data cache means responsive to instructions received from-said instruction cache means.
Claim 12
Dependent Claim
232 words
A microprocessor based computer system comprising: primary memory means for selectively storing and outputting digital information from an addressable high speed memory; a high speed systems. bus coupled to the primary memory means for communicating digital information between means coupled to said system bus; instruction cache means, coupled to said system bus, for managing the selective retrieval of instructions from said primary memory, and for selectively storing said instructions therefrom in a mapped addressable very high speed memory for providing selective very high speed output of said instructions from said high speed memory; data cache means, coupled to said system bus, for managing the selective storage and retrieval of data to and from said primary memory, and for selectively storing and outputting said data at very high speed to and from a mapped addressable very high speed memory; a very high speed instruction bus coupled to said instruction cache means for communicating said very high speed instruction output from said instruction cache along said instruction bus; a very high speed data bus coupled to said said data cache means for communicating data at said very high speed to and from said data cache means along said data bus; and microprocessor processing means, independently coupled to each of said instruction bus and said data bus, for selectively processing data received from said data cache means responsive to instructions received from-said instruction cache means.
Claim 13
Dependent Claim
22 words
The system as in Claim 10 wherein said microprocessor processing means outputs processed data at very high speed to said data bus.
Claim 14
Dependent Claim
25 words
The system as in Claim 10 further comprising: peripheral adapter means coupled to said system bus for providing system interface to an external peripheral device.
Claim 15
Dependent Claim
52 words
The system as in Claim 10 further comprising: bus arbiter means coupled to the system bus for selectively resolving channel access conflicts between selected other means coupled to the system bus and to the bus arbiter means, so as to prevent collisions and maintain the integrity of communications on said system bus.
Claim 16
Dependent Claim
47 words
The system as in Claim 10 further comprising: protocol conversion means, coupled to said system bus, for coupling to an external bus, for managing interface access and protocol conversion of digital information between any of said other means coupled to said system bus and said external bus.
Claim 17
Dependent Claim
65 words
The system as in Claim 10 further comprising: interrupt controller means coupled to said microprocessor processing means and independently and separately coupled to selected ones of said means which are coupled to the system bus, said interrupt controller means providing for the monitoring and prioritizing and resolving interrupt requests to said processing means from said selected ones of said means coupled to said system bus.
References Cited (Backward Citations)
No citation records indexed.
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