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EP0192139A2
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Frame buffer memory controller
Assignee: Tektronix Inc
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Filing: 1986-02-07
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Granted: —
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Expires: 2006-02-07
Abstract
Abstract A frame buffer memory controller (24) allows rapid image updating while maintaining screen refresh data flow rate. One frame buffer memory controller (24) controls one or more pixel depth columns comprising one or more frame buffer memory chips (22) per pixel. Each frame buffer memory controller (24) listens on a display processor bus (26) for read, write or read-modify-write commands addressed to a pixel, or memory chip, under its control. Such commands, along with the associated addresses and data, are stored in a first-in, first-out (FIFO) buffer (35) for execution during the first free memory cycle.
Inventors
- 👤 David L. Knierim
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 14:05
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
79 words
A frame buffer memory characterized by a plurality of memory units (22), each of said memory units corresponding to one bit of a pixel within a frame buffer word; a plurality of frame buffer memory controllers (24), each of said frame buffer memory controllers providing access to a subset of said memory units on a first-in, first-out basis; and means for addressing each of said frame buffer memory controllers (24) from a display processor via a display bus (26).
Claim 2
Dependent Claim
79 words
A frame buffer memory characterized by a plurality of memory units (22), each of said memory units corresponding to one bit of a pixel within a frame buffer word; a plurality of frame buffer memory controllers (24), each of said frame buffer memory controllers providing access to a subset of said memory units on a first-in, first-out basis; and means for addressing each of said frame buffer memory controllers (24) from a display processor via a display bus (26).
Claim 3
Dependent Claim
76 words
A frame buffer memory as recited in claim 1, characterized in that said frame buffer memory controllers (24) each comprise: means (34) for recognizing information on said display bus (26) directed to said subset of memory units controlled by said frame buffer memory controller (24); means (35) for preserving said information for execution on a first-in, first-out as available basis; and means (38,40,42) for transferring data to said memory units (22) from said preserving means (35).
Claim 4
Dependent Claim
40 words
A frame buffer memory as recited in claim 1 or 2, characterized in that said subset comprises n of said memory units (22) where n is the number of bits for each said pixel, each bit corresponding to a plane.
Claim 5
Dependent Claim
60 words
A frame buffer memory as recited in one of claims 1 to 3, characterized in that said subset comprises m x n of said memory units (22) where m is the number of said pixels controlled by said frame buffer memory controller (24) and n is the number of bits for each said pixel, each bit corresponding to a plane.
Claim 6
Dependent Claim
57 words
A frame buffer memory controller, characterized by: means (34) for recognizing information on a display bus (26), said information being addressed to a subset of a plurality of memory units (22); means (35) for temporarily storing said information on a first-in, first-out basis; and means (38,40,42) for transferring said information from said storing means to said subset.
Claim 7
Dependent Claim
57 words
A frame buffer memory controller, characterized by: means (34) for recognizing information on a display bus (26), said information being addressed to a subset of a plurality of memory units (22); means (35) for temporarily storing said information on a first-in, first-out basis; and means (38,40,42) for transferring said information from said storing means to said subset.
Claim 8
Dependent Claim
33 words
A frame buffer memory controller as recited in claim 5, characterized by means for addressing said subset to transfer said information to a video display on a non-interference basis with said transferring means.
References Cited (Backward Citations)
No citation records indexed.
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