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EP0187994A2
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Topologically-distributed-memory multiprocessor computer and method of electronic computation using said computer
Assignee: New York University
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Filing: 1985-12-20
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Granted: —
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Expires: 2005-12-20
Abstract
Abstract A nodular, expandable, topologically-distributed-memory multiprocessor computer comprises a plurality of non-directly communicating slave processors under the control of a synchronizer and a master processor. Memory space is partitioned into a plurality of memory cells. Dynamic variables may be mapped into the memory cells so that they depend upon processing in nearby partitions. Each slave processor is connected in a topologically well-defined way through a dynamic bi-directional switching system (gateway) to different respective ones of the memory cells. Access by the slave processors to their respective topologically similar memory cells occurs concurrently or in parallel in such a way that no data-flow conflicts occur. The topology of date distribution may be chosen to take advantage of symmetries which occur in broad classes of problems. The system may be tied to a hose computer used for data storage and analysis of data not efficiently processed by the multiprocessor computer.
Inventors
- 👤 Herbert Ruck Carleton
- 👤 Jeremy Quinton Broughton
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 20:42
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17337; G06F15/17343; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1652; G06F13/1657; G06F15/76; G06F15/80
Claims Analysis
Total Claims: 62
Claim 1
Independent Claim
42 words
A multiprocessor computer, comprising: a plurality of processors; a data memory space comprising a plurality of memory cells; and switching means for enabling ones of said plurality of processors to be connected, in parallel, to topologically similar ones of said memory cells.
Claim 2
Dependent Claim
42 words
A multiprocessor computer, comprising: a plurality of processors; a data memory space comprising a plurality of memory cells; and switching means for enabling ones of said plurality of processors to be connected, in parallel, to topologically similar ones of said memory cells.
Claim 3
Dependent Claim
34 words
A multiprocessor computer, as recited in Claim 1, wherein said switching means is adapted to enable said plurality of processors to be connected, in parallel, to alternate topologically similar ones of said memory cells.
Claim 4
Dependent Claim
45 words
A multiprocessor computer, as recited in Claim 2, further comprising synchronizing means cooperating with said switching means for synchronously and non-conflictingly causing to be connected, in parallel, ones of said plurality of slave processors to alternate topologically similar ones of said plurality of memory cells.
Claim 5
Dependent Claim
51 words
A multiprocessor computer, as recited in Claim 3, wherein said switching means is further adapted to enable to be connected at least one of said plurality of processors to a plurality of said memory cells and at least one of said plurality of memory cells to a plurality of said processors.
Claim 6
Dependent Claim
34 words
A multiprocessor computer, as recited in Claim 4, wherein said processors are slave processors and further comprising a master processor coupled to said plurality of processors for supervising the operation of said slave processors.
Claim 7
Dependent Claim
27 words
A multiprocessor computer, as recited in Claim 5, wherein said master processor is further coupled to said synchronizing means for supervising the operation of said synchronizing means.
Claim 8
Dependent Claim
23 words
A multiprocessor computer, as recited in Claim 5, wherein said slave processors communicate only indirectly, through the master processor and through shared memory.
Claim 9
Dependent Claim
27 words
S. A multiprocessor computer, as recited in Claim 5, wherein said switching means includes bi-directional controlled pathway elements across which said slave processors access said memory cells.
Claim 10
Dependent Claim
17 words
A multiprocessor computer, as recited in Claim 5, wherein said slave processors each comprise a bit-slice microprocessor.
Claim 11
Dependent Claim
16 words
A multiprocessor computer, as recited in Claim 5, wherein said slave processors comprise a Harvard architecture.
Claim 12
Dependent Claim
24 words
A multiprocessor computer, as recited in Claim 5, wherein ones of said slave processors and ones of said memory cells are in five-fold coordination.
Claim 13
Dependent Claim
24 words
A multiprocessor computer, as recited in Claim 5, wherein ones of said slave processors and ones of said memory cells are in four-fold coordination.
Claim 14
Dependent Claim
17 words
A multiprocessor computer, as recited in Claim 5, wherein problem space is partitioned into said memory cells.
Claim 15
Dependent Claim
15 words
A multiprocessor computer, as recited in Claim 5, wherein said slave processors are independently programmable.
Claim 16
Dependent Claim
20 words
A multiprocessor computer, as recited in Claim 5, wherein variables are mapped into memory space in relation to their values.
Claim 17
Dependent Claim
19 words
A multiprocessor computer, as recited in Claim 5, further comprising a host computer in communication with said master processor.
Claim 18
Dependent Claim
17 words
A multiprocessor computer, as recited in Claim 14, wherein said slave processors have their own instruction memory.
Claim 19
Dependent Claim
17 words
A multiprocessor computer, as recited in Claim 16, wherein said host computer serves as said master processor.
Claim 20
Dependent Claim
21 words
A multiprocessor computer, as recited in Claim 5, wherein said memory space is connected in a periodic fashion using boundary conditions.
Claim 21
Dependent Claim
84 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, a method of electronic computation comprising the steps of: (a) mapping problem space into said plurality of memory cells; (b) providing access for ones of said plurality of processors each to a non-conflicting topologically similar memory cell; and (c) processing, in parallel, data from said topologically similar memory cells using the respectively accessing ones of said plurality of processors.
Claim 22
Dependent Claim
84 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, a method of electronic computation comprising the steps of: (a) mapping problem space into said plurality of memory cells; (b) providing access for ones of said plurality of processors each to a non-conflicting topologically similar memory cell; and (c) processing, in parallel, data from said topologically similar memory cells using the respectively accessing ones of said plurality of processors.
Claim 23
Dependent Claim
104 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of electronic computation as recited in Claim 20 further comprising the steps of: (d) providing access for ones of said plurality of processors each to a non-conflicting, topologically similar memory cell, at least one of said plurality of processors being provided access to a memory cell other than the memory cell most recently accessed thereby; and (e) processing, in parallel, data from said topologically similar memory cells using the respectively accessing ones of said plurality of processors.
Claim 24
Dependent Claim
60 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of Claim 21 wherein during step (d), at least one of said plurality of memory cells is provided to be accessed by a processor other than the processor most recently provided access thereto.
Claim 25
Dependent Claim
41 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of Claim 22 further comprising the step of: (f) repeating steps (d) and (e).
Claim 26
Dependent Claim
53 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of electronic computation, as recited in Claim 23 wherein data in adjacent memory cells are processed in an overlapping manner by respective ones of said processors.
Claim 27
Dependent Claim
53 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of electronic computation, as recited in Claim 21 wherein during step (a) variables are mapped into memory cells in relation to the values of the variables.
Claim 28
Dependent Claim
48 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of electronic computation, as recited in Claim 25, wherein any of steps (a) through (f) are supervised by a master processor.
Claim 29
Dependent Claim
55 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of electronic computation, as recited in Claim 26, wherein during step (a), data is distributed to memory cells in such a manner to thereby partition the computational problem.
Claim 30
Dependent Claim
53 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of electronic computation, as recited in Claim 26, wherein during a slave processor execution cycle, data from a memory cell is passed to said master processor.
Claim 31
Dependent Claim
43 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of electronic computation, as recited in Claim 27, wherein step (a) is carried out using software.
Claim 32
Dependent Claim
48 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of electronic computation, as recited in Claim 27, wherein during step (a), a three-dimensional problem is mapped into data memory space.
Claim 33
Dependent Claim
47 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of electronic computation, as recited in Claim 21, wherein data in adjacent memory cells is processed in an overlapping manner.
Claim 34
Dependent Claim
42 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of electronic computation, as recited in Claim 23, wherein said slave processors execute different programs.
Claim 35
Dependent Claim
45 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of electronic computation, as recited in Claim 27, wherein variables are implicitly represented by their location in memory.
Claim 36
Dependent Claim
51 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of electronic computation, as recited in either of Claims 20 or 23, wherein memory space is connected in a periodic fashion using boundary conditions.
Claim 37
Dependent Claim
47 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of electronic computation, as recited in Claim 23, wherein processing between slave processors and memory cells occurs in five-fold coordination.
Claim 38
Dependent Claim
47 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of electronic computation, as recited in Claim 23, wherein processing between slave processors and memory cells occurs in four-fold coordination.
Claim 39
Dependent Claim
42 words
In a computer system comprising a plurality of processors and a data memory space which data memory space further comprises a plurality of memory cells, the method of electronic computation, as recited in Claim 23, wherein said slave processors execute similar programs.
Claim 40
Dependent Claim
16 words
A multiprocessor computer, as recited in Claim 8 wherein slave processor/gateway/memor y cell architecture is modular.
Claim 41
Dependent Claim
13 words
A multiprocessor computer, as recited in Claim 8, further comprising a pipelined architecture.
Claim 42
Dependent Claim
127 words
A multiprocessor computer, comprising: a plurality of slave processors; a data memory space partitioned into a plurality of memory cells; gateway means for switchably associating the individual ones of said slave processors each with a plurality of ones of said memory cells such that the individual ones of said memory cells are likewise switchably associated with a plurality of said individual ones of said slave processors; synchronizing means cooperating with said gateway means for synchronously, non-conflictingly and switchably causing to be connected the individual ones of their respective associated memory cells; and a master processor cooperating with said synchronizing means for causing said synchronizing means to alternatingly switchably connect the individual ones of said slave processors between different topologically similar ones of their respective associated memory cells.
Claim 43
Dependent Claim
127 words
A multiprocessor computer, comprising: a plurality of slave processors; a data memory space partitioned into a plurality of memory cells; gateway means for switchably associating the individual ones of said slave processors each with a plurality of ones of said memory cells such that the individual ones of said memory cells are likewise switchably associated with a plurality of said individual ones of said slave processors; synchronizing means cooperating with said gateway means for synchronously, non-conflictingly and switchably causing to be connected the individual ones of their respective associated memory cells; and a master processor cooperating with said synchronizing means for causing said synchronizing means to alternatingly switchably connect the individual ones of said slave processors between different topologically similar ones of their respective associated memory cells.
Claim 44
Dependent Claim
25 words
A multiprocessor computer, as recited in Claim 40, wherein said gateway means includes bi-directional controlled pathways across which said slave processors access said memory cells.
Claim 45
Dependent Claim
16 words
A multiprocessor computer, as recited in Claim 40, wherein said slave processors comprise a Harvard architecture.
Claim 46
Dependent Claim
20 words
A multiprocessor computer, as recited in Claim 40, wherein said slave processors comprise a processing unit and local instruction memory.
Claim 47
Dependent Claim
24 words
A multiprocessor computer, as recited in Claim 40, wherein ones of said slave processors and ones of said memory cells are in five-fold coordination.
Claim 48
Dependent Claim
24 words
A multiprocessor computer, as recited in Claim 40, wherein ones of said slave processors and ones of said memory cells are in four-fold coordination.
Claim 49
Dependent Claim
15 words
A multiprocessor computer, as recited in Claim 40, wherein said memory space is software configurable.
Claim 50
Dependent Claim
27 words
A multiprocessor computer, as recited in Claim 40, wherein said ones of said slave processors and ones of said memory cells are configured in a pipeline architecture.
Claim 51
Dependent Claim
21 words
A multiprocessor computer, as recited in Claim 40, wherein variables may be mapped into memory space in relation to their values.
Claim 52
Dependent Claim
19 words
A computer system comprising the multiprocessor computer of Claim 40, wherein slave processor/switching means/ memory cell design is modular.
Claim 53
Dependent Claim
16 words
A multiprocessor computer, as recited in Claim 40, wherein said master processor is a host computer.
Claim 54
Dependent Claim
21 words
A multiprocessor computer, as recited in Claim 40, wherein said memory space is connected in a periodic fashion using boundary conditions.
Claim 55
Dependent Claim
26 words
A multiprocessor computer, as recited in either of claims 1 or 40, further comprising means for reconfiguring said multiprocessor computer between parallel and concurrent processing modes.
Claim 56
Dependent Claim
41 words
A multiprocessor computer, comprising: a plurality of processors; a data memory space comprising a plurality of memory cells; and switching means for enabling ones of said plurality of processors to be connected concurrently to topologically similar ones of said memory cells.
Claim 57
Dependent Claim
41 words
A multiprocessor computer, comprising: a plurality of processors; a data memory space comprising a plurality of memory cells; and switching means for enabling ones of said plurality of processors to be connected concurrently to topologically similar ones of said memory cells.
Claim 58
Dependent Claim
33 words
A multiprocessor computer, as recited in Claim 53, wherein said switching means is adapted to enable said plurality of processors to be connected concurrently to alternate topologically similar ones of said memory cells.
Claim 59
Dependent Claim
44 words
A multiprocessor computer, as recited in Claim 54, further comprising synchronizing means cooperating with said switching means for synchronously and non-conflictingly causing to be connected concurrently ones of said plurality of slave processors to alternate topologically similar ones of said plurality of memory cells.
Claim 60
Dependent Claim
51 words
A multiprocessor computer, as recited in Claim 55, wherein said switching means is further adapted to enable to be connected at least one of said plurality of processors to a plurality of said memory cells and at least one of said plurality of memory cells to a plurality of said processors.
Claim 61
Dependent Claim
34 words
A multiprocessor computer, as recited in Claim 56, wherein said processors are slave processors and further comprising a master processor coupled to said plurality of processors for supervising the operation of said slave processors.
Claim 62
Dependent Claim
28 words
A multiprocessor computer, as recited in Claim 57, wherein a plurality of said slave processors and a plurality of said memory cells are linked, respectively, as pipeline elements.
References Cited (Backward Citations)
No citation records indexed.
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