EP0187518A2 — Data processor system and method

Claim 1

Independent Claim 260 words

A data processing system of the type having a system bus, including a bus clock, data input means for inputting data, display means for displaying inputted data and processed data, storage means for storing the input data and the processed data, and shared storage means connected to each of the above means through the system bus, said system executing data processing as designated by the data input means, wherein the system comprises (a) a plurality of memory bank means each connected to the system bus and constituting the shared storage means; (b) a plurality of separate processor means provided for each of the data input means, the display means and the data storage means, respectively, for separately executing data processing for each of said means, each of the separate processors being connected to the system bus and being capable of generating a memory request command signal on the system bus for the purpose of transferring data between designated memory bank means and said processor means; (c) means for generating an enable signal to acknowledge an occupation of one of said designated memory bank means in response to each memory request by any one of said processor means; and (d) executing means for dividing data transferred between said processor means and said memory bank means into predetermined groupings of divisional data and for executing data processing for each divisional data in synchronization with the bus clock of the system bus and in simultaneous parallel fashion when a plurality of memory requests are outputted simultaneously from a plurality of said processor means.

Claim 2

Dependent Claim 260 words

A data processing system of the type having a system bus, including a bus clock, data input means for inputting data, display means for displaying inputted data and processed data, storage means for storing the input data and the processed data, and shared storage means connected to each of the above means through the system bus, said system executing data processing as designated by the data input means, wherein the system comprises (a) a plurality of memory bank means each connected to the system bus and constituting the shared storage means; (b) a plurality of separate processor means provided for each of the data input means, the display means and the data storage means, respectively, for separately executing data processing for each of said means, each of the separate processors being connected to the system bus and being capable of generating a memory request command signal on the system bus for the purpose of transferring data between designated memory bank means and said processor means; (c) means for generating an enable signal to acknowledge an occupation of one of said designated memory bank means in response to each memory request by any one of said processor means; and (d) executing means for dividing data transferred between said processor means and said memory bank means into predetermined groupings of divisional data and for executing data processing for each divisional data in synchronization with the bus clock of the system bus and in simultaneous parallel fashion when a plurality of memory requests are outputted simultaneously from a plurality of said processor means.

Claim 3

Dependent Claim 80 words

The data processing system as set forth in claim 1, wherein said executing means comprises means for generating a sequence of separate timing signals ("time slots") synchronously with the bus clock of the system bus and for allocating each time slot to one of said memory bank and transferring a unit of processed data constituting the divisional data through the system bus at the timing of the time slot allocated to the memory bank means designated by the memory request.

Claim 4

Dependent Claim 61 words

The data processing system as set forth in claim 2, wherein said executing means comprises second means for transferring a unit of processed data for said memory bank means, other than that designated by the memory request, through the system bus at the timing of an allocated time slot corresponding to a memory bank means not designated by the memory request.

Claim 5

Dependent Claim 74 words

The data processing system as set forth in claim 3, wherein said executing means further comprises third means for forming a time slot allocated to no memory bank means in addition to the time slots allocated to a plurality of said memory bank means and for transferring a unit of processed data for the memory bank means designated by the memory request through the system bus at the timing of the non-allocated time slot.

Claim 6

Dependent Claim 61 words

The data processing system as set forth in claim 4, wherein said executing means comprises fourth means for transferring data corresponding to the memory request to the memory bank at the timing of the time slot next to an empty time slot, when an empty time slot not designated by the memory request is produced in a series of time slots.

Claim 7

Dependent Claim 44 words

The data processing system as set forth in claims 2 or 5, wherein the time slot is selected to have a time duration which is shorter than the time required for the memory cycle, required when the memory bank means writes or reads data.

Claim 8

Dependent Claim 47 words

The data processing system as set forth in claims 2 or 5, wherein the time slot is selected to have a time duration which is shorter than the data processing time reauired when one of said processors processes the data read by it through the system bus.

Claim 9

Dependent Claim 82 words

The data processing system as set forth in claims 1 or 5, wherein the system bus comprises an address bus for transferring address data to designate an address of memory location in said memory bank means to which the memory request is outputted; a write data bus for transferring write data to be written in the memory location designated by the address data; and a read data bus for transferring read data read from the memory location designated by the address data.

Claim 10

Dependent Claim 23 words

The data processing system as set forth in claims 1 or 5, wherein said processor means is comprised of a plurality of microprocessors.

Claim 11

Dependent Claim 23 words

The data processing system as set forth in claims 1 or 5, wherein said memory bank means is composed of a dynamic RAM.

Claim 12

Dependent Claim 74 words

The data processing system as set forth in claims 1, 2, 3, 4, or 5, which further comprises arbitrating means for selecting, in accordance with a priority order previously determined with respect to each processor means, one of a plurality of memory requests, which are outputted simultaneously from two 3 r more processor means to the same memory bank and for processing data corresponding to the memory request selected on the basis of priority.

Claim 13

Dependent Claim 45 words

The data processing system as set forth in claim 11, wherein said arbitratinq means comprises a lock function such that a selection of other memory requests are refused until data corresponding to one of the priority-selected memory requests have been processed by a predetermined amount.

Claim 14

Independent Claim 190 words

A method of processing data, the method being of the type having the steps of inputting data, storing data, processinq data, and displaying data wherein the improvement comprises the steps of (a) storing data in a nluralitv of memory banks which are connected to each other by a system bus; (b) separately processing data for each of the steps of inputting, storing, and displaying data, in separate data processors, each of the separate processing steps being carried out in part over the system bus, and generating a memory request command signal on the system bus for the purpose of transferring data between designated memory banks and the processors; (c) occupying the memory bank designated by the memory request while transferring data between one of the processors and the designated memory bank and generating an enable signal to acknowledge the occupation; and (d) simultaneously outputting a plurality of memory requests from a plurality of processors, dividing data transferred between the processors and the memory banks into predetermined groupings of divisional data, and processing each divisional data in synchronization with the bus clock of the system bus and in simultaneous parallel fashion.

Claim 15

Independent Claim 190 words

A method of processing data, the method being of the type having the steps of inputting data, storing data, processinq data, and displaying data wherein the improvement comprises the steps of (a) storing data in a nluralitv of memory banks which are connected to each other by a system bus; (b) separately processing data for each of the steps of inputting, storing, and displaying data, in separate data processors, each of the separate processing steps being carried out in part over the system bus, and generating a memory request command signal on the system bus for the purpose of transferring data between designated memory banks and the processors; (c) occupying the memory bank designated by the memory request while transferring data between one of the processors and the designated memory bank and generating an enable signal to acknowledge the occupation; and (d) simultaneously outputting a plurality of memory requests from a plurality of processors, dividing data transferred between the processors and the memory banks into predetermined groupings of divisional data, and processing each divisional data in synchronization with the bus clock of the system bus and in simultaneous parallel fashion.

Claim 16

Dependent Claim 82 words

The data processing method system as set forth in claim 13, wherein the divisional data processing step comprises the steps of generating a sequence of separate timing signals ("time slots") synchronously with the bus clock of the system bus and allocating each time slot to one of the memory banks and transferring a unit of processed data constituting the divisional data through the system at the time of the time slot allocated to the memory bank means designated by the memory request.

Claim 17

Dependent Claim 62 words

The data processing method as set forth in claim 14, wherein the divisional data processing step comprises the further step of transferring a unit of processed data for a memory bank, other than one designated by the memory request, through the system bus at the timing of an allocated time slot corresponding to a memory bank not designated by the memory reauest.

Claim 18

Dependent Claim 72 words

The data processing method as set forth in claim 15, wherein the divisional data processing step comprises the further step of forming a time slot allocated to no memory bank in addition to the time slots allocated to a plurality of the memory banks and transferring a unit of processed data for the memory bank designated by the memory request through the system bus at the timing of the non-allocated time slot.

Claim 19

Dependent Claim 64 words

The data processing method as set forth in claim 16, wherein the divisional data processing step comprises the further step of transferring data corresponding to the memory request to the memory bank at the timing of the time slot next to an empty time slot, when an empty time slot not designated by the memory request is produced in a series of time slots.

Claim 20

Dependent Claim 48 words

The data processinq method as set forth in claims 14, 15, 16 or 17, wherein the time slot is generated so as to have a time duration which is shorter than the time required for the memory cycle required to read or write data in the memory bank.

Claim 21

Dependent Claim 48 words

The data processing method as set forth in claims 14, 15, 16 or 17, wherein the time slot is generated so as to have a time duration which is shorter than the time required to process data read through the system bus in the separate data processing steps.

Claim 22

Dependent Claim 70 words

The data processing method as set forth in claim 13, which further comprises the step of arbitrating between concurrent requests by selecting in accordance with a priority order previously determined with respect to each processor, one of a plurality of memory requests, which are outputted simultaneously from two or more processors to the same memory bank and processing data corresponding to the memory request selected on the basis of priority.

Claim 23

Dependent Claim 44 words

The data processing method as set forth in claim 20, wherein arbitrating step comprises a locking step during which the selection of other memory requests is refused until data corresponding to one of the priority-selected memory requests have been processed by a predetermined amount.

Data processor system and method

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