A microprocessor device with variable memory capacity

Claim 2

A microprocessor comprising a command execution unit (1) which executes various commands; an address output logic (2) which outputs memory address to be accessed to an address bus; a data input/output logic (3) which exchanges instructions and data between said command execution unit (1) and a data bus; and a bus controller (4) which outputs control signals from said command execution unit (1) to a control bus, characterized in that: a bus cycle changeover circuit (10) is connected between said command execution unit (1) and each of said address output logic (2), said data input/output logic (3), and said bus controller (4), and that said bus cycle changeover circuit (10) controls timing and address in order to transmit/receive data to/from a part of data bus according to a data width selection signal and a data width selection instruction.

Claim 3

A microprocessor as claimed in claim 1, wherein the bus cycle changeover circuit (10) comprises a cycle control circuit (11) which outputs data width instruction based on data width selection signal, a memory access instruction depending on to the data width, and a signal expressing the latter half access cycle, an upper/lower selection circuit (12) which selects upper/lower part of the data bus according to the signal expressing the latter half access cycle, a data bus changeover circuit (13, 14, 15) which transmits/receives data to/from the data bus according to the output of said upper/lower selection circuit, an address adder circuit (17) which adds address value according to said signal expressing the latter half access cycle, and a shift circuit (16) which shifts the output of said address adder circuit according to said data width selection signal.

Claim 4

A microprocessor as claimed in claim 2, wherein said data bus changeover circuit comprises an upper selection circuit (13) which transmits/receives the upper data to/from the upper part of the data bus without any modification, a lower selection circuit (14) which transmits/receives the lower data to/from the lower part of the data bus without any modificatiton, and a switching circuit (15) which permits data transfer between the upper part of the bus and the lower part of the bus when the data bus is used by narrowing.

Claim 5

A microprocessor as claimed in claim 1, wherein the data bus width is switched between the whole width and half of the width.

Claim 6

A microprocessor as claimed in claim 1, wherein said data width selection signal is depending on the data width recognized by writing predetermined data into the predetermined memory address, then by reading the data from the predetermined memory address, and by checking the success in the access operation.