Semiconductor device and method for manufacturing the same

Claim 1

A semiconductor device comprising source and drain regions (45, 46) between whi.ch a channel region is formed, a gate insulating layer (35) provided on said channel region, a floating gate (43) provided on said gate insulating layer, a composite insulating layer (25a, 25b) provided on said floating gate and including a plurality of insulating layers which are different from one another in their properties, and a control gate (44) provided on said composite insulating layer, characterized in that the end portions of said composite insulating layer (25a, 25b) extend in the length direction of said channel region beyond the end portions of at least one of said floating and control gates (43, 44). c

Claim 8

A method of manufacturing a semiconductor device having floating and control gates (43, 44) which further includes source and drain regions (45, 46), a channel region, and a composite insulating layer (25a) provided between said floating and control gates, characterized by comprising the steps of: selecting first and second regions on a semiconductor substrate (31) of a first conductivity type, said source and drain regions (45, 46) being formed in said first and second regions; forming a field insulating layer (34) surrounding an active region including said first and second regions; forming a first Si0 2 (silicon dioxide) layer (35) covering said active region; forming a first polysilicon layer (36) covering said first Si0 2 layer (35) and said field insulating layer (34); patterning said first polysilicon layer so as to have a width corresponding to the width of said floating gate (43), said width being the length in the channel-width direction; forming a multilayered insulating layer (25) on said first polysilicon layer from which said composite insulating layer (25a) is formed; forming a second polysilicon layer (41) on said multilayered insulating layer (25); forming a resist pattern (42) on said second polysilicon layer (41), said resist pattern having a length corresponding to that of said composite insulating layer (25a), said length being the length in the channel-length direction; effecting an etching, using said resist pattern (42) as a mask, for forming said control gate (44), said composite insulating layer (25a) and said floating gate so as to have an equal length; shortening the lengths of said control and floating gates; and doping an impurity of second conductivity type into said first and second regions for forming said source and drain regions (45, 46).

Claim 9

A method of manufacturing a semiconductor device having floating and control gates (43, 44) which further includes source and drain regions (45, 46), a channel region, and a composite insulating layer (25a) provided between said floating and control gates, characterized by comprising the steps of: selecting first and second regions on a semiconductor substrate (31) of a first conductivity type, said source and drain regions (45, 46) being formed in said first and second regions; forming a field insulating layer (34) surrounding an active region including said first and second regions; forming a first Si0 2 (silicon dioxide) layer (35) covering said active region; forming a first polysilicon layer (36) covering said first Si0 2 layer (35) and said field insulating layer (34); patterning said first polysilicon layer so as to have a width corresponding to the width of said floating gate (43), said width being the length in the channel-width direction; forming a multilayered insulating layer (25) on said first polysilicon layer from which said composite insulating layer (25a) is formed; forming a second polysilicon layer (41) on said multilayered insulating layer (25); forming a resist pattern (42) on said second polysilicon layer (41), said resist pattern having a length corresponding to that of said composite insulating layer (25a), said length being the length in the channel-length direction; effecting an etching, using said resist pattern (42) as a mask, for forming said control gate (44), said composite insulating layer (25a) and said floating gate so as to have an equal length; shortening the lengths of said control and floating gates; and doping an impurity of second conductivity type into said first and second regions for forming said source and drain regions (45, 46).

Claim 14

A method of manufacturing a semiconductor device having floating and control gates (43, 44) which further includes source and drain regions (45, 46), a channel region, and a composite insulating layer (25a) provided between said floating and control gates, characterized by comprising the steps of: selecting first and second regions on a semiconductor substrate (31) of a first conductivity type, said source and drain regions (45, 46) being formed in said first and second regions; forming a field insulating layer (34) surrounding an active region including said first and second regions; forming a first SiO 2 (silicon dioxide) layer (35a) covering said active region; forming a laminated layer (27) including a first polysilicon layer (36a) covering said first Si0 2 layer (35a) and said field insulating layer (34), a second Si0 2 layer (38a) covering said first polysilicon layer, a silicon nitride layer (39a) covering said second Si0 2 layer, and a third Si0 2 layer (40a) covering said silicon nitride layer; patterning said laminated layer (27) so as to have a width corresponding to the width of said floating gate (43), said width being the length in the channel-width direction; making the ends (50) of said patterned silicon nitride layer (39a) extend in the channel-width direction beyond the ends of said patterned first polysilicon layer by a thermal treatment; forming a second polysilicon layer (41a) on said laminated layer (27); forming a resist pattern (42) on said second polysilicon layer (41a), said resist pattern having a length corresponding to that of said composite insulating layer (25a); etching, by anisotropic etching method and using said resist pattern as a mask, said second polysilicon layer (41a), said third Si0 2 layer (40a), said silicon nitride layer (39a), said second Si0 2 layer (38a) and said first polysilicon layer (36a), subsequently; shortening the lengths of said second polysilicon layer (41a) and said first polysilicon layer (36a); and doping an impurity of a second conductivity type into said first and second regions for forming said source and drain regions (45, 46).

Claim 15

A method of manufacturing a semiconductor device having floating and control gates (43, 44) which further includes source and drain regions (45, 46), a channel region, and a composite insulating layer (25a) provided between said floating and control gates, characterized by comprising the steps of: selecting first and second regions on a semiconductor substrate (31) of a first conductivity type, said source and drain regions (45, 46) being formed in said first and second regions; forming a field insulating layer (34) surrounding an active region including said first and second regions; forming a first SiO 2 (silicon dioxide) layer (35a) covering said active region; forming a laminated layer (27) including a first polysilicon layer (36a) covering said first Si0 2 layer (35a) and said field insulating layer (34), a second Si0 2 layer (38a) covering said first polysilicon layer, a silicon nitride layer (39a) covering said second Si0 2 layer, and a third Si0 2 layer (40a) covering said silicon nitride layer; patterning said laminated layer (27) so as to have a width corresponding to the width of said floating gate (43), said width being the length in the channel-width direction; making the ends (50) of said patterned silicon nitride layer (39a) extend in the channel-width direction beyond the ends of said patterned first polysilicon layer by a thermal treatment; forming a second polysilicon layer (41a) on said laminated layer (27); forming a resist pattern (42) on said second polysilicon layer (41a), said resist pattern having a length corresponding to that of said composite insulating layer (25a); etching, by anisotropic etching method and using said resist pattern as a mask, said second polysilicon layer (41a), said third Si0 2 layer (40a), said silicon nitride layer (39a), said second Si0 2 layer (38a) and said first polysilicon layer (36a), subsequently; shortening the lengths of said second polysilicon layer (41a) and said first polysilicon layer (36a); and doping an impurity of a second conductivity type into said first and second regions for forming said source and drain regions (45, 46).