Patent EP0187237A2 successfully refreshed from Google Patents.
EP0187237A2
Expired / Lapsed
EP
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dRAM cell and method
Assignee: Texas Instruments Inc
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Filing: 1985-11-22
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Granted: —
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Expires: 2005-11-22
Abstract
Abstract A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate. The transistor source and drain are insulated from the substrate, and the transistor may be adjacent the trench or on the upper portion of the trench sidewalls. Signal charge is stored on the capacitor plate insulated from the substrate.
Inventors
- 👤 Pallab K. Chatterjee
- 👤 William F. Richardson
- 👤 Satwinder Malhi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 16:30
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/39; H10B12/395; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0383
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
37 words
1 . A memory cell in a semiconductor substrate, comprising: (a) a capacitor formed in a trench in said substrate; and ( b ) a field effect transistor formed in said trench and connected to said capacitor.
Claim 2
Dependent Claim
37 words
1 . A memory cell in a semiconductor substrate, comprising: (a) a capacitor formed in a trench in said substrate; and ( b ) a field effect transistor formed in said trench and connected to said capacitor.
Claim 3
Dependent Claim
42 words
The cell of Claim 1, wherein: (a) said capacitor is located primarily in the lower portion of said trench; and (b) said transistor channel is located primarily in the upper portion of said trench and oriented so channel conduction is substantially vertical.
Claim 4
Dependent Claim
15 words
The cell of Claim 2, wherein: (a) said trench has a substantially convex cross section.
Claim 5
Dependent Claim
16 words
The cell of Claim 2, wherein: (a) said channel is substantially adjacent to said trench sidewalls.
Claim 6
Dependent Claim
24 words
The cell of Claim 4, wherein: (a) the upper portion of said trench has a larger diameter than the lower portion of said trench.
Claim 7
Dependent Claim
18 words
The cell of Claim 2, wherein: (a) said channel is formed in semiconductor material inserted into said trench.
Claim 8
Dependent Claim
20 words
The cell of Claim 2, wherein: (a) said channel is formed in a portion of the sidewalls of said trench.
Claim 9
Dependent Claim
39 words
The cell of Claim 7, wherein: (a) said capacitor is characterized by one plate including a portion of the sidewalls of said trench and the other plate including material inserted into said trench and conductively connected to said channel.
Claim 10
Dependent Claim
105 words
A memory cell array on a substrate, comprising: (a) a plurality of parallel first conductor lines on said substrate: (b) a plurality of parallel second conductor lines crossing said first conductor lines but insulated therefrom; and (c) a plurality of cells, one cell at each of said crossings, each of said cells including a field effect transistor and a capacitor in a trench in said substrate below said crossing, said transistor drain connected to one of said first conductor lines, said transistor gate connected to one of said second conductor lines, and said transistor source connected to a first of the plates of said capacitor.
Claim 11
Dependent Claim
105 words
A memory cell array on a substrate, comprising: (a) a plurality of parallel first conductor lines on said substrate: (b) a plurality of parallel second conductor lines crossing said first conductor lines but insulated therefrom; and (c) a plurality of cells, one cell at each of said crossings, each of said cells including a field effect transistor and a capacitor in a trench in said substrate below said crossing, said transistor drain connected to one of said first conductor lines, said transistor gate connected to one of said second conductor lines, and said transistor source connected to a first of the plates of said capacitor.
Claim 12
Dependent Claim
21 words
The array of Claim 9, wherein: (a) a second of the plates of said capacitor is connected to said substrate. .
Claim 13
Independent Claim
120 words
A method of fabricating a one transistor/one capacitor in a semiconductor substrate trench memory cell, comprising the steps of: (a) forming a first region in and adjacent the surface of said substrate and of a conductivity type opposite that of said substrate; ( b ) forming a trench in said substrate and through said first region; (c) forming an insulating layer on the walls of said trench; and (d) forming a semiconductor layer in said trench and on said insulating layer, said semiconductor layer forming the source, channel, and drain of said transistor and one of the plates of said capacitor, said first region forming the gate of said transistor, and said substrate forming the other plate of said capacitor.
Claim 14
Independent Claim
120 words
A method of fabricating a one transistor/one capacitor in a semiconductor substrate trench memory cell, comprising the steps of: (a) forming a first region in and adjacent the surface of said substrate and of a conductivity type opposite that of said substrate; ( b ) forming a trench in said substrate and through said first region; (c) forming an insulating layer on the walls of said trench; and (d) forming a semiconductor layer in said trench and on said insulating layer, said semiconductor layer forming the source, channel, and drain of said transistor and one of the plates of said capacitor, said first region forming the gate of said transistor, and said substrate forming the other plate of said capacitor.
Claim 15
Independent Claim
144 words
A method of fabricating a one transistor/one capacitor in a substrate trench memory cell, comprising the steps of: (a) forming a first trench in said substrate; (b) forming transistor gate insulator on the walls and bottom of said first trench; (c) filling said first trench with transistor gate material; (d) forming a second trench in said substrate, said second trench formed through said transistor gate material in said first trench, said second trench narrower than said first trench so that not all of said gate material is removed upon formation of said second trench, said second trench extending into said substrate from the bottom of said first trench; (e) forming a capacitor plate/transistor source region in the walls of said second trench; (f) forming capacitor insulator on the walls of said second trench; and (g) forming second capacitor plate material on said capacitor insulator.
Claim 16
Independent Claim
144 words
A method of fabricating a one transistor/one capacitor in a substrate trench memory cell, comprising the steps of: (a) forming a first trench in said substrate; (b) forming transistor gate insulator on the walls and bottom of said first trench; (c) filling said first trench with transistor gate material; (d) forming a second trench in said substrate, said second trench formed through said transistor gate material in said first trench, said second trench narrower than said first trench so that not all of said gate material is removed upon formation of said second trench, said second trench extending into said substrate from the bottom of said first trench; (e) forming a capacitor plate/transistor source region in the walls of said second trench; (f) forming capacitor insulator on the walls of said second trench; and (g) forming second capacitor plate material on said capacitor insulator.
Claim 17
Independent Claim
92 words
A method of fabricating a one transistor/one capacitor in a semiconductor substrate trench memory cell, comprising the steps of: (a) forming a trench in said substrate; (b) forming an insulating layer on the walls of said trench; (c) filling the bottom portion of said trench with semiconductor material; and (d) forming a field effect transistor in the unfilled upper portion and sidewalls of said trench, the source of said transistor formed by partially filling said upper portion adjacent said material, said material and said source together including one plate of said capacitor.
Claim 18
Independent Claim
92 words
A method of fabricating a one transistor/one capacitor in a semiconductor substrate trench memory cell, comprising the steps of: (a) forming a trench in said substrate; (b) forming an insulating layer on the walls of said trench; (c) filling the bottom portion of said trench with semiconductor material; and (d) forming a field effect transistor in the unfilled upper portion and sidewalls of said trench, the source of said transistor formed by partially filling said upper portion adjacent said material, said material and said source together including one plate of said capacitor.
References Cited (Backward Citations)
No citation records indexed.
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