Semiconductor memory device

Claim 2

A semiconductor memory device comprising a plurality of memory cells arranged in a semiconductor substrate, each of said memory cells having an insulated gate type field effect transistor and a capacitor element coupled with said transistor, said transistor including a channel region provided along a side wall.of a trench formed in said substrate, and said capacitor element including a dielectric film formed in said trench.

Claim 3

A semiconductor memory device of claim l, in which said side wall of said trench is substantially perpendicular . to a major surface of said substrate, and said dielectric film extends substantially in parallel with said side wall.

Claim 4

A semiconductor memory device comprising a semiconductor substrate of one conductivity type having a major surface, a plurality of trenches formed in said substrate and extending from said major surface into said substrate, and a plurality of memory cells each having one insulated gate type field effect transistor and one capacitor element coupled with said transistor, said transistor including a first impurity region of the opposite conductivity type formed in said substrate adjacent to one of said trenches, a second impurity region of the opposite conductivity type formed in said substrate adjacent to said one of said trenches at a position separate from., Said first impurity region, a gate insulating film formed along the side wall of said trench between said first and second impurity regions, a gate electrode formed on said gate insulating film along said trench on the side opposite to said first and second impurity regions, and a channel region formed in said substrate between said first and second impurity regions and positioned along said side wall of said trench, said capacitor element including a first electrode formed on said gate electrode with an insulating layer interposed therebetween, said first electrode being elongated along the side wall of said trench and connected to said second impurity'region, a dielectric film formed on said first electrode and constituting an inner wall of said trench, and a second electrode formed on said dielectric film in said trench.

Claim 5

A semiconductor memory device comprising a semiconductor substrate of one conductivity type having a major surface, a plurality of trenches formed in said substrate and extending from said major surface into said substrate, and a plurality of memory cells each having one insulated gate type field effect transistor and one capacitor element coupled with said transistor, said transistor including a first impurity region of the opposite conductivity type formed in said substrate adjacent to one of said trenches, a second impurity region of the opposite conductivity type formed in said substrate adjacent to said one of said trenches at a position separate from., Said first impurity region, a gate insulating film formed along the side wall of said trench between said first and second impurity regions, a gate electrode formed on said gate insulating film along said trench on the side opposite to said first and second impurity regions, and a channel region formed in said substrate between said first and second impurity regions and positioned along said side wall of said trench, said capacitor element including a first electrode formed on said gate electrode with an insulating layer interposed therebetween, said first electrode being elongated along the side wall of said trench and connected to said second impurity'region, a dielectric film formed on said first electrode and constituting an inner wall of said trench, and a second electrode formed on said dielectric film in said trench.

Claim 6

A semiconductor memory device of claim 3 in which said gate electrode, said first electrode and said second electrode are made of polycrystalline silicon, respectively.

Claim 7

A semiconductor device of claim 3, in which each of said channel region, said gate insulating film, said gate electrode, said first electrode and said dielectric film has a ring shape in the plan view.

Claim 8

A semiconductor memory device of claim 3 further comprising a third impurity region of said one conductivity type and having a higher impurity concentration than that of said substrate, said third impurity region being provided under said second impurity region and extended to a part of said channel region.

Claim 9

A semiconductor memory device of claim 3, in Which said second electrode of said capacitor element is connected to a bit line, and said gate electrode of said transistor is connected to a word line.

Claim 10

A semiconductor memory device of claim 3, in which said first impurity region of said transistor is connected to a bit line, and said gate electrode of said transistor is connected to a word line.