Patent EP0186150A2 successfully refreshed from Google Patents.
EP0186150A2
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EP
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Parallel processing computer
Assignee: Hitachi Ltd
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Filing: 1985-12-19
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Granted: —
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Expires: 2005-12-19
Abstract
Abstract A plurality of operation units (1, 2, 3) are connected to one another. The operation units include a processor (1), a buffer memory (2), and a data transfer control circuit (3) connected between the processor (1) and the buffer memory (2) for controlling the data input-output with the buffer memories in the other of the operation units. The buffer memories (2) and the data transfer control circuits (3) are connected with one another by data buses (201, 202 and 310, 320), respectively.
Inventors
- 👤 Fumio Takahashi
- 👤 Yukio Nagaoka
- 👤 Iwao Harada
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 22:06
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/76; G06F15/80; G06F15/8007; G06F15/8015; G06F15/163; G06F15/173; G06F15/17337
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
87 words
A parallel processing computer comprising a plurality of operation units (1, 2, 3) connected to one another, wherein said operation units include a processor (1), a buffer memory (2), and a data transfer control circuit (3) connected between the processor (1) and the buffer memory (2) for controlling the data input-output with said buffer memories (2) in the other of said operation units, said buffer memories (2) and said data transfer control circuit (3) being connected with one another by data buses (201, 202, 310, 320), respectively.
Claim 2
Dependent Claim
87 words
A parallel processing computer comprising a plurality of operation units (1, 2, 3) connected to one another, wherein said operation units include a processor (1), a buffer memory (2), and a data transfer control circuit (3) connected between the processor (1) and the buffer memory (2) for controlling the data input-output with said buffer memories (2) in the other of said operation units, said buffer memories (2) and said data transfer control circuit (3) being connected with one another by data buses (201, 202, 310, 320), respectively.
Claim 3
Dependent Claim
37 words
The parallel processing computer according to claim 1, wherein each of said processors (1) stores data in each of said connected buffer memories (2) and sets the number of words to be transferred between said operation units.
Claim 4
Dependent Claim
64 words
The parallel processing computer according to claim 1, wherein a plurality of said operation units (1, 2, 3) are arranged two-dimensionally by connecting said operation units with one another on each row and column, and said computer further comprises at least one bus connection mechanism(S i )which connects in series the operation units of an arbitrary number of rows or columns with one another.
Claim 5
Dependent Claim
88 words
The parallel processing computer according to claim 3 wherein a plurality of said bus connection mechanisms (S i ) are disposed in such a manner as to correspond to each row or column, and each of said bus connection mechanisms (S i ) consists of four switching circuits (61-64) having the input and output terminals thereof connected to the buses of said operation units or to the other of said bus connection mechanisms and a control circuit (54) controlling the operation of each of said switching circuits (61-64).
Claim 6
Dependent Claim
39 words
The parallel processing computer according to claim 4 wherein said control circuit (54) in said bus connection mechanism (S i ) is subjected simultaneously to open and closing control by a bus connection signal (bC) from one control processor.
References Cited (Backward Citations)
No citation records indexed.
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