Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
215 words
A semiconductor memory device having a plurality of memory cells arranged in a matrix formed by word lines and bit lines connected to a data bus (DB, DB), and comprising: a plurality of blocks (BK i0 , ---, BK ik ) provided by dividing each bit line (BL i , BL i ) and each including a plurality of memory cells (C i00 , ---, C i0m ; ---; C ik0' ---,C ikm ),a sense amplifier (VSA i0 , ---, VSA im ), and a switching element (S i0 , S i0 ; - - - ; S ik' S ik ) inserted into each bit line, means responsive to the selection of a memory cell to be accessed for activating only the sense amplifier of the block containing the selected memory cell; and means controlling the switching elements after activation of the sense amplifier of said selected block containing the selected memory cell, to make ON only the switching elements of the selected block and of each block eventually located between the selected block and the data bus, characterised in that the driving abilities of the sense amplifiers (VSA i0 , ---; VSA in ) are different from each other and increase as the distance between the corresponding blocks and the data bus increases.
Claim 2
Dependent Claim
215 words
A semiconductor memory device having a plurality of memory cells arranged in a matrix formed by word lines and bit lines connected to a data bus (DB, DB), and comprising: a plurality of blocks (BK i0 , ---, BK ik ) provided by dividing each bit line (BL i , BL i ) and each including a plurality of memory cells (C i00 , ---, C i0m ; ---; C ik0' ---,C ikm ),a sense amplifier (VSA i0 , ---, VSA im ), and a switching element (S i0 , S i0 ; - - - ; S ik' S ik ) inserted into each bit line, means responsive to the selection of a memory cell to be accessed for activating only the sense amplifier of the block containing the selected memory cell; and means controlling the switching elements after activation of the sense amplifier of said selected block containing the selected memory cell, to make ON only the switching elements of the selected block and of each block eventually located between the selected block and the data bus, characterised in that the driving abilities of the sense amplifiers (VSA i0 , ---; VSA in ) are different from each other and increase as the distance between the corresponding blocks and the data bus increases.
Claim 3
Dependent Claim
93 words
A semiconductor memory device according to claim 1, characterized in that each sense amplifier comprises a plurality of MOS (Metal Oxide Semiconductor) transistors with a channel size which increases as the distance between the corresponding blocks and the data bus increases, whereby the transistors in the farthest block have the widest channel size to confer to the sense amplifier in said farthest block the highest driving ability whereas the transistors in the nearest block have the smallest channel size to confer to the sense amplifier in said nearest block the lowest driving ability.