Random access memory

Claim 2

Random access memory array having a plurality of memory cells connected between a pair of bit lines (BL; BR), word lines and decoders, circuit means connected to said plurality of memory cells for selecting any predetermined one of said plurality of memory cells, write circuit means connected to said pair of bit lines for writing data into said selected predetermined one of said plurality of memory cells, characterized by an end of write shut down circuit connected between the write circuit means and said pair of bit lines, said "end of write circuit means" promptly deactivating said write circuit means upon the completion of the writing of data into said selected predetermined one of said plurality of memory cells.

Claim 3

Random access memory array, as recited in claim 1, wherein said end of write shut down circuit deactivates the write circuit at least slightly in anticipation of the completion of the writing of data into said selected predetermined one of said plurality of memory cells.

Claim 4

Random access memory array as recited in claim 1, characterized by m pairs of word/drain lines, each pair of word/drain lines containing a word line (WL) and a drain line, each row of memory cells being associated with a discrete one of said m pairs of word/drain lines, and each memory cell of each row of memory cells being connected between the word line and drain line of the pair of word/drain lines associated with the row of memory cells; by m write "0" circuits, each of said m write "0" circuits being connected to the first bit line of a discrete one of said m bit line pairs; by a first group of m end of write circuits, each of said first group of m end of write circuits being connected between a discrete one of said m write "0" circuits and the second bit line of the bit line pair associated with said discrete one of said m write "0" circuits; by m write "1" circuits, each of said m write "1" circuits being connected to the second bit line of a discrete one of said m bit line pairs; and by a second group of m end of write circuits, each of said second group of m end of write circuits being connected between a discrete one of said m write "1" circuits and the first bit line of the bit line pair associated with said discrete one of said m write 1" circuits.

Claim 5

Random access memory array, as recited in ciaim 3, wherein, each of said m write "0" circuits includes a write "0" transistor, each of said m write "1" circuits includes a write "1" transistor, each end of write circuit of said first group of m end of write circuits is connected to the write "0" transistor of the write "0" circuit with which it is associated, and each end of write circuit of said second group of m end of write circuits is connected to the write "1" transistor of the write 1" circuit with which it is associated.

Claim 6

Random access memory array, as recited in ciaim 3, wherein, each of said m write "0" circuits includes a write "0" transistor, each of said m write "1" circuits includes a write "1" transistor, each end of write circuit of said first group of m end of write circuits is connected to the write "0" transistor of the write "0" circuit with which it is associated, and each end of write circuit of said second group of m end of write circuits is connected to the write "1" transistor of the write 1" circuit with which it is associated.

Claim 7

Random access memory array, as recited in claim 4, wherein each end of write circuit of said first group of m end of write circuits and each end of write circuit of said second group of m end of write circuits respectively comprise essentially unilaterally conductive circuit means.

Claim 8

Random access memory array, as recited in claim 5, wherein each of said unilaterally conductive circuit means consists essentially of at least one diode.

Claim 9

Random access memory array, as recited in claim 5, wherein each of said unilaterally conductive circuit means comprises first and second serially connected Schottky diodes.

Claim 10

Random access memory array, as recited in claim 1, characterized by m pairs of bit lines (BL; BR), each pair of bit lines containing a first bit line and a second bit line, each column of memory cells being associated with a discrete one of said m pairs of bit lines, and each memory cell of each column of memory cells being connected between the first bit line and the second bit line of the pair of bit lines associated with the column of memory cells; by n pairs of word/drain lines, each pair of word/drain lines containing a word line (WL) and a drain line, each row of memory cells being associated with a discrete one of said n pairs of word/drain lines, and each memory cell of each row of memory cells being connected between the word line and drain line of the pair of word/drain lines associated with the row of memory cells; by m write "0" circuits, each of said m write "0" circuits being associated with a discrete one of said m bit line pairs and connected to the first bit line of said discrete one of said m bit line pairs; by a first group of m end of write circuits, each one of said first group of m end of write circuits being connected between a discrete one of said m write "0" circuits and the second bit line of the bit line pair associated with said discrete one of said m write "0" circuits; by m write "1" circuits, each of said m write "1" circuits being associated with a discrete one of said m bit line pairs and connected to the second bit line of said discrete one of said m bit line pairs; by a second group of m end of write circuits, each one of said second m end of write circuits being connected between a discrete one of said m write "1" circuits and the first bit line of the bit line pair associated with said discrete one of said m write "1" circuits; by word-drain line selection circuit means, said word-drain line selection circuit means in response to receipt of a word-drain line address selecting any predetermined pair of said n pairs of word-drain lines; by bit line pair selection circuit means, said bit line pair selection circuit means in response to receipt of a bit line pair selection address selecting any predetermined pair of said m pairs of bit lines; by controllable circuit means, said controllable circuit means connected to said m write "0" circuits and said m write "1" circuits and cooperating with said word-drain line selection means and said bit-line pair selection circuit means, said controllable circuit means initiating either a "write operation" or a "read operation" whereby during a "write operation" a bit ("1" or "0") will be written (stored) into a selected memory cell and during a "read operation" a bit ("1" or "0") will be read from a selected memory cell; and by sense amplifier circuit means connected to said m pair of bit lines, said sense amplifier electrically manifesting the binary bit ("1" or "0") read during a "read operation".

Claim 11

Random access memory array, as recited in claims 1 and 8, wherein each memory cell is a complementary transistor switch (CTS) memory cell.

Claim 12

Random access memory array, as recited in claim 8, wherein each of said memory cells is an unclamped complementary transistor switch (CTS) memory cell, each of said unclamped CTS memory cells being characterized by first and second transistors of a first conductivity type, said first and second transistors each having an emitter, base and collector, said emitters of said first and second transistors respectively connected to the drain line of said discrete one of said n pairs of word-drain lines, by third and fourth transistors of a second conductivity type, said third and fourth transistors each having an emitter, base and collector, said emitter of said third transistor and said emitter of said fourth transistor being respectively connected to said word line of said discrete one of said n pairs of word-drain lines, said collector of said third transistor connected to said base of said first transistor, said base of said third transistor connected in common to said collector of said first transistor and said base of said second transistor, said collector of said fourth transistor connected to said base of said second transistor, said base of said fourth transistor connected in common to said collector of said second transistor and said base of said first transistor, and by first and second diodes, said first diode connected between said base of said third transistor and the first bit line of said discrete one of said m pairs of bit lines, and said second diode connected between said base of said fourth transistor and said second bit line of said discrete one of said m pairs of bit lines.

Claim 13

Random access memory array, as recited in claim 11, wherein said word-drain line selection circuit means includes n identical write enhancement circuit means for enhancing the "write operation" of said memory array, each of said n identical write enhancement circuit means being a two terminal device and each of said n identical circuit means being connected between the word line and the drain of a discrete one of said n pairs of word-drain lines.

Claim 14

Random access memory array, as recited in claim 12, wherein each of said n identical write enhancement circuit means is a two terminal unilaterally conductive device.

Claim 15

Random access memory array, as recited in claim 12, wherein each of said n identical write enhancement circuit means is a pn diode.

Claim 16

Random access memory array, as recited in claim 12, wherein each of said n identical write enhancement circuit means is a diode connected transistor.

Claim 17

Random access memory array, as recited in claim 12, wherein each of said n identical write enhancement circuit means is a two terminal device comprising a first terminal connected to the base of a transistor and a second terminal connected in common to the collector and emitter of said transistor.