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EP0185137A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Storage masking circuit and method for a multiprocessor system

Assignee: International Business Machines Corp
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Filing: 1985-08-20
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Granted: —
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Expires: 2005-08-20
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Abstract

Abstract A masking circuit for a multiprocessor system is disclosed. In the multiprocessor system, a first command status register contains information associated with a first processor of the multiprocessor system and a second command status register contains information associated with a second processor of the multiprocessor system. Normally, the command status registers contain command information related to the processing of commands for their respective processors. However, during a flush operation, wherein data stored in the cache of a second processor is flushed to a main memory in order to allow access to the data by a first processor, the command being executed by the first processor must be blocked in order to allow the flush operation to be completed. When the flush operation is complete, the execution of the command by the first processor commences. The first command status register contains the command being executed by the first processor, and the second command status register contains information related to the need for a flush operation. The masking circuit of the present invention senses the existence of the command in the first command status register and the information, related to the flush operation, in the second command status register and masks the command in the first command status register from the multiprocessor system until the flush operation (as indicated by the contents of the second command status register) is complete. When the command is masked, the execution of the command is postponed until the flush operation is completed. When the flush operation is complete, the second command status register is reset. When reset, the multiprocessor system is permitted to commence execution of the command.

Inventors

  • 👤 Patrick Francis Dutton
  • 👤 Earl Whitney Jackson, Jr.

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-26 05:52
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 95 words
A system including a first storage means for storing information therein and a second storage means for storing other information therein, said system comprising: masking circuit means connected to said first storage means and to said second storage means for sensing the existence of said information stored in said first storage means and the existence of said other information stored in said second storage means and for masking the existence of said information in said first storage means from said system until said other information in said second storage means is executed by said system.
Claim 2
Independent Claim 95 words
A system including a first storage means for storing information therein and a second storage means for storing other information therein, said system comprising: masking circuit means connected to said first storage means and to said second storage means for sensing the existence of said information stored in said first storage means and the existence of said other information stored in said second storage means and for masking the existence of said information in said first storage means from said system until said other information in said second storage means is executed by said system.
Claim 3
Dependent Claim 71 words
The system of claim 1, further comprising: further circuit means connected to said masking circuit means and responsive to an output signal generated therefrom for releasing the mask imposed by said masking circuit means on said first storage means when execution of said other information by said system is complete, said system executing said information stored in said first storage means when said mask is released by said further circuit means.
Claim 4
Dependent Claim 188 words
A multiprocessor system wherein a desired page of data in the cache of a second processor is flushed to and stored in a main memory in response to a clock signal energizing said second processor and a clock signal energizing said main memory, said desired page of data stored in said main memory being utilized by a first processor in the execution of an instruction, said multiprocessor system comprising: first circuit means for storing information therein associated with said first processor of said multiprocessor system; second circuit means for storing information therein associated with said second processor of said multiprocessor system; and third circuit means connected to said first and said second circuit means and responsive to output signals developed therefrom for sensing the existence of said information stored in said first circuit means, for sensing the existence of said information stored in said second circuit means and for masking said information stored in one of said first and second circuit means from said multiprocessor system thereby permitting said information stored in the other of said first and second circuit means to be executed by said multiprocessor system.
Claim 5
Dependent Claim 188 words
A multiprocessor system wherein a desired page of data in the cache of a second processor is flushed to and stored in a main memory in response to a clock signal energizing said second processor and a clock signal energizing said main memory, said desired page of data stored in said main memory being utilized by a first processor in the execution of an instruction, said multiprocessor system comprising: first circuit means for storing information therein associated with said first processor of said multiprocessor system; second circuit means for storing information therein associated with said second processor of said multiprocessor system; and third circuit means connected to said first and said second circuit means and responsive to output signals developed therefrom for sensing the existence of said information stored in said first circuit means, for sensing the existence of said information stored in said second circuit means and for masking said information stored in one of said first and second circuit means from said multiprocessor system thereby permitting said information stored in the other of said first and second circuit means to be executed by said multiprocessor system.
Claim 6
Dependent Claim 75 words
The multiprocessor system of claim 3, further comprising: fourth circuit means connected to said third circuit means for releasing the mask associated with said one of said first and second circuit means when said information stored in the other of said first and second circuit means has been executed by said multiprocessor system thereby permitting said information stored in said one of said first and second circuit means to be executed by said multiprocessor system.

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