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EP0184827A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

A high speed and high power transistor

Assignee: NEC Corp
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Filing: 1985-12-11
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Granted: —
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Expires: 2005-12-11
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Abstract

Abstract @ A high speed and high power transistor includes a first layer of a first semiconductor material, a second layer of a second semiconductor material formed on the first layer, the second semiconductor material having a smaller electron affinity than the first semiconductor material, first and second electrode positioning on ends of the second layer, respectively, in contact with the first layer, and a control electrode formed on the second layer between the first and second electrodes the control electrode injecting holed into the second layer in accordance with an input signal to induce an electron channel between the first and second electrodes.

Inventors

  • 👤 Keiichi Ohata
  • 👤 Hikaru Hida
  • 👤 Masaki Ogawa

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-25 21:52
CPC Classifications
H; H10; H10D; H10D12/00

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 100 words
A transistor comprising: a first semiconductor layer of a first semiconductor material; a second semiconductor layer of a second semiconductor material formed on said first semiconductor layer, said second semiconductor material having a smaller electron affinity than said first semiconductor material; a means coupled to said second semiconductor layer for injecting holes into said second semiconductor layer to induce an electron channel on the surface of said first semiconductor layer at the boundary between said first and second semiconductor layers; and first and second electrodes formed in contact with said first and second semiconductor layers to interpose said electron channel.
Claim 2
Dependent Claim 100 words
A transistor comprising: a first semiconductor layer of a first semiconductor material; a second semiconductor layer of a second semiconductor material formed on said first semiconductor layer, said second semiconductor material having a smaller electron affinity than said first semiconductor material; a means coupled to said second semiconductor layer for injecting holes into said second semiconductor layer to induce an electron channel on the surface of said first semiconductor layer at the boundary between said first and second semiconductor layers; and first and second electrodes formed in contact with said first and second semiconductor layers to interpose said electron channel.
Claim 3
Dependent Claim 20 words
A transistor as claimed in claim 1, wherein said first and second semiconductor material are undoped or slightly N-type material.
Claim 4
Dependent Claim 20 words
A transistor as claimed in claim 2, wherein said first semiconductor material is GaAs, said second semiconductor material being AlGaAs.
Claim 5
Dependent Claim 21 words
A transistor as claimed in claim 1, wherein said injecting means includes a PN junction formed in said second semiconductor layer.
Claim 6
Dependent Claim 55 words
A transistor as claimed in claim 1, wherein said second semiconductor layer has a surface layer of N-type GaAs and said injecting means includes a P-type semi- bonductor layer of a material selected from a group of AlGaAs and GaAs which is disposed on said surface of N-type GaAs to form a PN junction therebetween.
Claim 7
Dependent Claim 36 words
A transistor as claimed in claim 5, wherein said P-type semiconductor layer of said injecting means is extended over said surface layer of said second semiconductor layer to cover the same as a surface passivation layer.
Claim 8
Dependent Claim 106 words
A transistor comprising: a semi-insulating substrate; a first layer of undoped or slightly N-type GaAs formed on said semi-insulating substrate; a second layer of undoped or slightly N-type AlGaAs formed on said first layer; first and second electrodes formed at both ends of $aid second layer in contact with said second layer; and a control electrode of P-type AlGaAs formed on said second layer between said first and second electrodes, said control electrode injecting holes into said second layer in accordance with an input signal applied thereto to induce an electroh channel between said first and second electrodes in the surface region of said first layer.
Claim 9
Dependent Claim 106 words
A transistor comprising: a semi-insulating substrate; a first layer of undoped or slightly N-type GaAs formed on said semi-insulating substrate; a second layer of undoped or slightly N-type AlGaAs formed on said first layer; first and second electrodes formed at both ends of $aid second layer in contact with said second layer; and a control electrode of P-type AlGaAs formed on said second layer between said first and second electrodes, said control electrode injecting holes into said second layer in accordance with an input signal applied thereto to induce an electroh channel between said first and second electrodes in the surface region of said first layer.
Claim 10
Dependent Claim 124 words
A transistor comprising: a semi-insulating substrate; a first layer of undoped or slightly N-type GaAs formed on said semi-insulating substrate; a second layer of N-type Al x Ga 1-x As formed on said first layer, Said Al x Ga 1-x As continuously changing the value x from a predetermined value to zero as separating from said first layer; : first and second electrodes positioning at both ends of said second layer, respectively, in contact with said second layer; a third electrode of P-type GaAs formed on said second layer, said third electrode injecting holes into said second layer in accordance with an input signal applied thereto to induce an electron channel between said first and second.electrodes at the surface region of said first layer.
Claim 11
Dependent Claim 124 words
A transistor comprising: a semi-insulating substrate; a first layer of undoped or slightly N-type GaAs formed on said semi-insulating substrate; a second layer of N-type Al x Ga 1-x As formed on said first layer, Said Al x Ga 1-x As continuously changing the value x from a predetermined value to zero as separating from said first layer; : first and second electrodes positioning at both ends of said second layer, respectively, in contact with said second layer; a third electrode of P-type GaAs formed on said second layer, said third electrode injecting holes into said second layer in accordance with an input signal applied thereto to induce an electron channel between said first and second.electrodes at the surface region of said first layer.

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