Patent EP0184222A2 successfully refreshed from Google Patents.
EP0184222A2
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MOS type integrated circuit having charging and discharging transistors
Assignee: Toshiba Corp
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Filing: 1985-12-06
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Granted: —
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Expires: 2005-12-06
Abstract
Abstract A MOS integrated circuit includes one charging transistor (T1) and one discharging transistor (T2). One end of the current path of the charging transistor (T1) is connected to one end of the current path of the discharging transistor (T2). A high power voltage (VDD) is applied to the other end of the current path of the charging transistor (T1). The charging transistor (T1) charges one end thereof to a predetermined voltage level. A low power voltage (VSS) is applied to the other end of the current path of the discharging transistor (T2). The discharging transistor (T2) discharges one end thereof to the predetermined voltage level. Each transistor (T1, T2) includes layers (17, 19, 27, 29) of a low impurity concentration for weakening the surface electric field of the transistors (T1, T2), thereby reducing generation of hot electrons or impact ionization current. More hot electrons are generated in the charging transistor (T1) than in the discharging transistor (T2). The weakening layers (27, 29) of the discharging transistor (T2) has, therefore, an impurity concentration higher than the weakening layers (17, 19) of the charging transistor (T1).
Inventors
- 👤 Hiroyuki C/O Patent Division Kinoshita
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 14:29
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/603; H10D62/00; H10D62/60; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/8311; H10D84/8312; H10D84/85
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
118 words
A M OS type semiconductor integrated circuit having charging and discharging transistors comprising at least one first transistor (Tl) having at least one weakening layer (17, 19) for weakening a surface electric field of said first transistor, and a second transistor (T2) of which the current path is related at one end to one end of the current path of said first transistor, said second transistor having at least one weakening layer (27, 29) for weakening a surface electric field of said second transistor, characterized in that an impurity concentration of said electric field weakening layer (27, 29) of said second transistor is higher than that of said electric field weakening layer (17, 19) of said first transistor.
Claim 2
Dependent Claim
118 words
A M OS type semiconductor integrated circuit having charging and discharging transistors comprising at least one first transistor (Tl) having at least one weakening layer (17, 19) for weakening a surface electric field of said first transistor, and a second transistor (T2) of which the current path is related at one end to one end of the current path of said first transistor, said second transistor having at least one weakening layer (27, 29) for weakening a surface electric field of said second transistor, characterized in that an impurity concentration of said electric field weakening layer (27, 29) of said second transistor is higher than that of said electric field weakening layer (17, 19) of said first transistor.
Claim 3
Dependent Claim
128 words
The integrated circuit according to claim 1, characterized in that each of said first and second transistors (Tl, T2) includes a semiconductor substrate (11), a first layer (13, 15) formed in said semiconductor substrate (11) and serving as a drain, and a second layer (15, 25) formed in said semiconductor substrate (11) and serving as a source, said weakening layer (17) of said first transistor (Tl) is formed in at least said surface region of said semiconductor substrate (11) and in contact with said first layer (13) of said first transistor (Tl), and said weakening layer (27) of said second transistor (T2) is formed in at least said surface region of said semiconductor substrate (11) and in contact with said first layer (15) of said second transistor (T2).
Claim 4
Dependent Claim
208 words
The semiconductor integrated circuit according to claim 1, characterized in that said first and second transistors (Tl, T2) each includes a semiconductor substrate (11), a first layer (13, 15) formed in said semiconductor substrate (11) and serving as a drain, and a second layer (15, 25) formed in said semiconductor substrate (11) and serving as a source, said at least one weakening layer of said first transistor (Tl) includes a first weakening layer (17), said first weakening layer (17) formed in at least the surface region of said semiconductor substrate (11) and in contact with said first layer (13) of said first transistor (Tl), and a second weakening layer (19) formed in at least the surface region of said semiconductor substrate (11) and in contact with said second layer (15) of said first transistor (Tl), and said at least one weakening layer of said second transistor (T2) includes a first weakening layer (27) formed in at least surface region of said semiconductor substrate (11) and in contact with said first layer (15) of said second transistor (T2), and a second weakening layer (29) formed in at least the surface region of said semiconductor substrate (11) and in contact with said second layer (25) of said second transistor (T2).
Claim 5
Dependent Claim
109 words
The semiconductor integrated circuit according to claim 2, characterized in that said first transistor (Tl) is a MOS transistor with an LDD (Lightly Doped Drain-Source) structure having said electric field weakening layer (17), said weakening layer (17) being provided in the surface region of said semiconductor substrate (11) and in contact with said first layer (13) of said first transistor (Tl), and said second transistor (T2) is a MOS transistor with an LDD structure having said electric field weakening layer (27), said weakening layer (27) being provided in the surface region of said semiconductor substrate (12) and in contact with said first layer (15) of said second transistor (T2).
Claim 6
Dependent Claim
78 words
The semiconductor integrated circuit according to claim 3, characterized in that said first transistor (Tl) is a MOS transistor with an LDD structure having said first and second weakening layers (17, 19) which are provided in the surface regions of said semiconductor substrate (11), and said second transistor (T2) is a MOS transistor with an LDD structure having said first and second weakening layers (27, 29) which are provided in the surface regions of said semiconductor substrate (11).
Claim 7
Dependent Claim
69 words
The semiconductor integrated circuit according to claim 2, characterized in that said first transistor (Tl) is a MOS transistor with an GDD (Graded Diffused Drain-Source) structure having said weakening layer (81) covering said first layer (13) of said first transistor (Tl), and said second transistor (T2) is a MOS transistor with an GDD structure having said weakening layer (85) covering said first layer (15) of said second transistor (T2).
Claim 8
Dependent Claim
90 words
The semiconductor integrated circuit according to claim 3, characterized in that said first transistor (Tl) is a MOS transistor with a GDD structure having said first weakening layer (81) covering said first layer (13) of said first transistor (Tl) and said second weakening layer (83) covering said second layer (15), and said second transistor (T2) is a MOS transistor with a GDD structure having said first weakening layer (85) covering said first layer (25) of said second transistor (T2) and said second weakening layer (87) covering said second layer (25).
Claim 9
Dependent Claim
76 words
The semiconductor integrated circuit according to any one of claims 1 to 7, characterized in that an impurity concentration of said at least one weakening layer (17, 19) of said first transistor (Tl) is from 10 16 /cm 3 to 10 18 /cm 3 , and an impurity concentration of said at least one weakening layer (27, 29) of said second transistor (T2) is from 10 17 /cm 3 to 1 0 19 /cm 3 .
Claim 10
Dependent Claim
128 words
The semiconductor integrated circuit according to any one of claims 1 to 8, characterized in that said first transistor (Tl) is a charging transistor receiving at the other end of its current path a first predetermined voltage (VDD), said charging transistor being for charging said one end of the current path of said first transistor (Tl) to a second voltage equal or lower than said first voltage, and said second transistor (T2) is a discharging transistor receiving at the other end of its current path a third voltage lower than said second voltage, said discharging transistor being for discharging said one end of the current path of said second transistor (T2) to a fourth voltage equal or higher than said third voltage but lower than said second voltage.
Claim 11
Dependent Claim
103 words
The semiconductor integrated circuit according to any one of claims 2 to 9, characterized in that said first and second semiconductor layers (13, 15, 25) of said first and second transistors (Tl, T2) have substantially equal impurity concentrations, impurity concentrations of said weakening layer (27, 29) of said second transistor (T2) are lower than those of said first and second semiconductor layers (13, 15, 25) of said first and second transistors (Tl, T2), and an impurity concentration of said weakening layer (17, 19) of said first transistor (Tl) is lower than that of said weakening layer (27, 29) of said second transistor (T2).
References Cited (Backward Citations)
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