Patent EP0183185A2 successfully refreshed from Google Patents.
EP0183185A2
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Differential reference voltage generator for NMOS single-supply integrated circuits
Assignee: TIM SpA
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Filing: 1985-11-21
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Granted: —
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Expires: 2005-11-21
Abstract
Abstract Voltage reference is generated by a current generator which, trough a current-mirror amplifier, biases an enhancement MOS transistor as well as a depletion one, so that the desired voltage is equal to the difference between their threshold voltages.
Inventors
- 👤 Franco Salerno
- 👤 Mario Sartori
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 10:39
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F3/242; G05F3/245
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
191 words
1) Differential reference voltage generator for NMOS single-supply integrated circuits, characterized in that it comprises: - a first MOS depletion transistor (MD1) having gate and source connected together, and drain connected with power supply (V DD ); - a second MOS depletion transistor (MD2) having drain connected with power supply and gate connected with the source of the first transistor; - a third MOS enhancement transistor (ME1) having drain and gate connected together and with the source of the first transistor; - a fourth MOS enhancement transistor (ME2) having drain and gate connected together and with the source of the second transistor; - a fifth MOS enhancement transistor (ME3) having drain and gate connected together and with the source of the third transistor and having its source grounded; - a sixth MOS enhancement transistor (ME4) having drain connected with the source of the fourth transistor; the source grounded; and gate connected with the gate of the fifth transistor; said differential reference voltage being the difference between the voltage present at the source of the second transistor (MD2) and that present at the gate of the fifth and sixth transistor (ME3, ME4).
Claim 2
Dependent Claim
191 words
1) Differential reference voltage generator for NMOS single-supply integrated circuits, characterized in that it comprises: - a first MOS depletion transistor (MD1) having gate and source connected together, and drain connected with power supply (V DD ); - a second MOS depletion transistor (MD2) having drain connected with power supply and gate connected with the source of the first transistor; - a third MOS enhancement transistor (ME1) having drain and gate connected together and with the source of the first transistor; - a fourth MOS enhancement transistor (ME2) having drain and gate connected together and with the source of the second transistor; - a fifth MOS enhancement transistor (ME3) having drain and gate connected together and with the source of the third transistor and having its source grounded; - a sixth MOS enhancement transistor (ME4) having drain connected with the source of the fourth transistor; the source grounded; and gate connected with the gate of the fifth transistor; said differential reference voltage being the difference between the voltage present at the source of the second transistor (MD2) and that present at the gate of the fifth and sixth transistor (ME3, ME4).
Claim 3
Dependent Claim
75 words
2) Generator as in claim 1, characterized in that said second and third transistors (MD2, ME1) are dimensioned so that the product of parameters B, K of the second transistor is equal to the product of parameters β, K of the third transistor, where β = µ · C ox , with µ = charge-carrier mobility and C ox = specific gate capacity; K = W/L, with W and L channel cross-section and length respectively.
References Cited (Backward Citations)
No citation records indexed.
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