Semiconductor memory device with shift registers for high speed reading and writing

Claim 2

A semiconductor memory device comprising: a random-access memory having a memory cell array, a plurality of bit lines, and a plurality of word lines; a pair of shift registers adapted to be connected with said plurality of bit lines; transfer gate means arranged between said plurality of bit lines and said shift registers; and parallel data transfer means provided between said shift registers for carrying out the parallel data transfer between said shift registers.

Claim 3

A device according to claim 1, wherein said parallel data transfer means comprises logic gates for effecting logic processing of the data to be transferred.

Claim 4

A device according to claim 2, wherein said logic gates consist of exclusive OR gates.

Claim 5

A device according to claim 3, wherein an additional shift register is provided at the input side of said logic gates.

Claim 6

A semiconductor memory device comprising: a random-access memory having a memory cell array, a plurality of bit lines, and a plurality of word lines; a shift register for output for carrying out serial reading, data for one word line registered in parallel from said memory cell array into said shift register for output being delivered serially from said shift register for output; a shift register for input for registering data for one word line supplied serially from an external data source; a parallel data transfer means for carrying out logic processing of the data registered in said shift register for output and said shift register for input; and an instruction decoder for delivering an instruction for a selected logic which should be executed in said parallel data transfer means; the data for one word line to be supplied to said shift register for input and an operation code for instructing a selected logic to be supplied to said instruction decoder being able to be serially transmitted; the data for one word line obtained as the result of the processing in said parallel data transfer means according to said instructed selected logic being able to be written into the memory cells of a selected word line in said memory cell array.

Claim 7

A semiconductor memory device comprising: a random-access memory having a memory cell array, a plurality of bit lines, and a plurality of word lines; a shift register for output for carrying out serial reading, data for one word line registered in parallel from said memory cell array into said shift register for output being delivered serially from said shift register for output; a shift register for input for registering data for one word line supplied serially from an external data source; a parallel data transfer means for carrying out logic processing of the data registered in said shift register for output and said shift register for input; and an instruction decoder for delivering an instruction for a selected logic which should be executed in said parallel data transfer means; the data for one word line to be supplied to said shift register for input and an operation code for instructing a selected logic to be supplied to said instruction decoder being able to be serially transmitted; the data for one word line obtained as the result of the processing in said parallel data transfer means according to said instructed selected logic being able to be written into the memory cells of a selected word line in said memory cell array.

Claim 8

A device according to claim 5, wherein said parallel data transfer means consists of assemblies of parallel data transferring circuits.