Single transistor electrically programmable device and method

Claim 2

An electrically erasable programmable memory device comprising a body of single crystalline semiconductive material having a source and a drain; a first layer of insulating material on said body; a floating gate on said first layer of insulating material; a second layer of insulating material on said floating gate; a gate over said second layer of insulating material; and wherein said source is formed of a deep region of a first material and a shallower region of the first material and a second material, and the drain is formed of a shallow region of the second material; and further wherein the first material is selected to optimize capacitive coupling between the floating gate and the source.

Claim 3

The device of claim 1 wherein the second layer of insulating material comprises a layer of thermal oxide and a layer of tantalum pentoxide.

Claim 4

The device of claim 1 wherein the first layer of insulating material comprises oxynitride.

Claim 5

The device of claim 2 wherein the first layer has a thickness between 100 and 200 angstroms.

Claim 6

The device of claim 2 wherein the floating gate comprises a material having small grain size.

Claim 7

The device of claim 1 wherein the second material is arsenic and the first material is phosphorous.

Claim 8

The device of claim 1 wherein the floating gate has a symmetrical cross section relative to a axis normal to the body and which is uniformly spaced from the body.

Claim 9

The device of claim 7 wherein the gate has a symmetrical cross section relative to the normal axis.

Claim 10

The device of claim 2 wherein the layer of thermal oxide has a thickness of approximately 150 angstroms.

Claim 11

The device of claim 2 wherein the layer of tantalum pentoxide is approximately 500 angstroms thick.

Claim 12

The device of claim 2 wherein the layer of tantalum pentoxide is oxide rich.

Claim 13

An electrically erasable memory device having a plurality of storage sites, a plurality of row address lines, a plurality of column address lines, and a plurality of erase lines, wherein each combination of one of the plurality of row address lines and one of the plurality of column address lines define a different one of the plurality of storage sites, and further wherein each of the plurality of storage sites comprises a single transistor including a source coupled to an associated one of the plurality of erase lines; a drain coupled to an associated one of the plurality of column address lines; a control gate coupled to an associated one of the plurality of row address lines; and a floating gate positioned between the gate and the source and drain; and further including means for injecting hot electrons onto the floating gate when the associated ones of the column address and row address lines are raised to a first predetermined potential above that of the associated one of the erase line; and means for inducing Fowler-Nordheim tunneling of electrons from the floating gate to the source when the associated erase line is raised to a second predetermined potential above the associated row address line.

Claim 14

An electrically erasable memory device having a plurality of storage sites, a plurality of row address lines, a plurality of column address lines, and a plurality of erase lines, wherein each combination of one of the plurality of row address lines and one of the plurality of column address lines define a different one of the plurality of storage sites, and further wherein each of the plurality of storage sites comprises a single transistor including a source coupled to an associated one of the plurality of erase lines; a drain coupled to an associated one of the plurality of column address lines; a control gate coupled to an associated one of the plurality of row address lines; and a floating gate positioned between the gate and the source and drain; and further including means for injecting hot electrons onto the floating gate when the associated ones of the column address and row address lines are raised to a first predetermined potential above that of the associated one of the erase line; and means for inducing Fowler-Nordheim tunneling of electrons from the floating gate to the source when the associated erase line is raised to a second predetermined potential above the associated row address line.

Claim 15

The device of claim 12 wherein the injecting means comprise a first layer of insulating material positioned between the gate and the floating gate, said insulating material having a high dielectric constant to provide a high capacitance between the gate and floating gate; and a second layer of insulating material positioned between the floating gate and the source and drain said second layer having a low thickness so as to permit Fowler-Nordheim tunneling while optimizing the capacitive coupling between the floating gate and the source.

Claim 16

The device of claim 13 wherein the dielectric constant of the first layer is greater than 5.

Claim 17

The device of claim 14 wherein the thickness of the second layer is less than 200 angstroms.

Claim 18

The device of claim 14 wherein the first layer includes tantalum pentoxide.

Claim 19

The device of claim 14 wherein the first layer includes oxide rich tantalum pentoxide.

Claim 20

The device of claim 15 wherein the second layer comprises oxynitride.

Claim 21

The device of claim 14 wherein the first layer comprises a sandwich including a layer of tantalum pentoxide and a layer of thermal oxide.

Claim 22

The device of claim 19 wherein the tantalum pentoxide layer is approximately 500 angstroms thick.

Claim 23

The device of claim 19 wherein the thermal oxide layer is approximately 150 angstroms thick.

Claim 24

The device of claim 13 wherein the tunneling means include a source diffusion having a portion which underlies the floating gate so as to accept electrons which have tunneled through the second layer from the floating gate, said source diffusion having a smooth curvature so that gate- aided junction breakdown voltages are increased.

Claim 25

The device of claim 22 wherein the source diffusion comprises a shallow diffusion of arsenic; and a deep diffusion of phosphorus.

Claim 26

The device of claim 12 wherein the plurality of storage sites are arranged in an array to form rows and columns of storage sites, and further wherein the erase line associated with each of the plurality of storage sites are connected in common; the column address line for each of the storage sites in a column are connected in common; and the row address line for each of the storage sites in a row are connected in common.

Claim 27

The device of claim 24 wherein the transistors in the storage sites in each of the columns are positioned so that the source of any one transistor in a column is coupled to the source of an adjacent transistor in the same column and the drain of the one transistor is coupled to the drain of a different adjacent transistor in the same column.

Claim 28

The device of claim 13 wherein the first layer of insulating material comprises a sandwich of tantalum pentoxide and thermal oxide, the second layer of material comprises oxynitride, and the control gate and floating gate each comprise polysilicon.

Claim 31

The method of claim 27 wherein the second selected material implanting step includes the step of high voltage implanting phosphorous, and the first selected material implanting step includes the step of implanting arsenic.

Claim 32

The method of claim 27 wherein the first semiconductive material depositing step includes the step of growing a layer of oxynitride on the body.

Claim 33

The method of claim 29 wherein the oxynitride growing step includes the step of growing an oxide layer of a predetermined thickness; and thermally nitridizing the oxide layer.

Claim 34

The method of claim 30 wherein the oxide layer growing step includes the step of ending the growing step when the oxide layer reaches a thickness of between 100 and 200 angstroms.

Claim 35

The method of claim 30 wherein the nitridizing step includes the steps of placing the device in an atmosphere of ammonia and argon; raising the ambient temperature to approximately 1050 degrees; and maintaining the temperature for approximately 10 minutes.

Claim 36

The method of claim 27 wherein the floating gate is further fabricated of doped polysilicon, and the first layer of semiconductive material depositing step comprises the step of depositing silicon onto the first insulating layer; and doping the silicon as the silicon is being deposited to form an in situ doped layer of poly silicon.

Claim 37

The method of claim 33 wherein in the silicon depositing and the doping steps SiH 4 is combined with PH 3 at approximately 850°C in dry oxygen to provide the doped layer of polysilicon.

Claim 38

The method of claim 34-wherein the second layer of insulating material growing step includes the steps of growing a thin layer of oxide on the first layer of semiconductive material; reactively sputtering a layer of tantalum onto the thin oxide layer; and using argon and oxygen as the sputtering gas.

Claim 39

The method of claim 35 wherein the ratio of argon to oxygen in the sputtering gas is approximately 4 to 1.

Claim 40

The method of claim 36 wherein the reactive sputtering step is to form a slightly oxide rich deposition of tantalum pentoxide.

Claim 41

The method of claim 37 wherein the oxygen component of the tantalum pentoxide is in the range of 0 5 . 25 to O 5.5 .

Claim 42

The method of claim 35 wherein the thin layer oxide growing step is terminated when the thin oxide layer reaches a thickness of approximately 150 angstroms.

Claim 43

The method of claim 35 wherein the reactive sputtering step is terminated when the thickness of the layer reaches approximately 500 angstroms.

Claim 46

The method of claim 41 wherein the programming step includes the steps of raising the drain potential to a level between 4 and 6 volts above that of the source, and raising the gate potential to a level between 10 and 12 volts above the source.

Claim 47

The device of claim 12 wherein the plurality of storage sites are arranged in an array to form rows and columns of sites, in which the column address lines for each of the storage sites in a column of sites are connected in common, and the row address line for each of the storage sites in a row are connected in common, and the storage sites of each row are arranged in bytes; and further wherein the bytes of storage sites are arranged in columns of bytes; and the erase lines associated with each of the storage sites in a particular column of bytes are connected in common; so that a column of bytes can be erased at one time.

Claim 48

The device of claim 12 wherein the plurality of storage sites are arranged in an array to form rows and columns of sites, in which the storage sites of each row are arranged in bytes, the row address lines for each of the storage sites in a row are connected in common, and the column address lines for each of the storage sites in a column of sites are connected in common; and further wherein the bytes of storage sites are arranged in columns of bytes and a different one of a plurality of column select lines is associated with each column of bytes; further including a plurality of means, each associated with a particular byte and coupled to the row address line that is associated with the particular byte, for selecting the particular byte; wherein each selecting means is responsive to the column select line associated with the column in which the particular byte resides, and further wherein each selecting means is coupled to the erase lines for the storage sites in the byte with which said selecting means is associated and also coupled to the erase lines of the storage sites in an adjacent byte within the same column: so that a single byte can be erased at one time by raising the column select line for the column in which the byte to be erased resides to a first potential, floating all column address lines associated with said column, and raising the row address line for the associated adjacent byte within said column to a second potential less than said first potential.