Logic analyzer

Claim 2

A logic analyzer in which first input data is loaded into a first data memory (18) for each change in state of the data; it is detected by a first trigger detector (19)- that the first input data reaches a preset value; the detected output is delayed by first delay means (22) for a preset time; by the delayed output, the data loading into the first data memory is stopped; second input data is loaded into a second data memory (31); it is detected by a second trigger detector (32) that the second input data reaches a -preset value; the detected output is delayed by second delay means (33) for a presets time; and by the delayed output, the data loading into the second data memory is stopped, characterized by the provision of: a first data loading interval measuring circuit (45) for measuring the intervals of loading of the first input data into the first data memory (18); a first data loading interval memory (48) for storing the data loading intervals measured by the first data loading interval measuring circuit; a time difference measuring circuit (51) for measuring the time difference between the points of generation of the delayed outputs from the first and second delay means; a time difference memory (52) for storing the time difference measured by the time difference measuring circuit; specifying means (34, 36) for specifying desired one of the data loaded into one of the first and second data memories; and corresponding data detecting means (34) for obtaining data in the other data memory corresponding to the point of loading of the data specified by the specifying means, using the time difference stored in the time difference memory and the data loading intervals stored in the first data loading interval memory.

Claim 3

A logic analyzer according to claim 1 wherein the second input data is loaded into the second data memory with a fixed period.

Claim 4

A logic analyzer according to claim 2 wherein the corresponding data detecting means comprises reference time interval computing means for computing, as a reference time interval, the time interval between the loading of the specified data and the stopping of the data loading into the data memory in which the specified data is stored, and means whereby the time interval between the stopping of the data loading of the other data memory and each data loading thereinto and the time difference stored in the time difference memory are added including its sign, obtaining data corresponding to that one of the added values which is close to the reference time interval.

Claim 5

A logic analyzer according to claim 3 wherein the reference time interval computing means is a means whereby when the specified data is in the first data memory, the successive data loading intervals stored in the first data loading interval memory during the time between the loading of the specified data and the stopping of data loading into the first data memory, are added together to obtain the referehce time interval, and whereby when the specified data is in the second data memory, the number of data inputs into the second data memory during the time between the loading of the specified data and the stopping of the data loading into the second data memory and its data loading period are multiplied to obtain the reference time interval, and wherein the corresponding data detecting means is a means whereby when the specified data is in the first data memory, a value K is obtained which makes the sum of K times of the fixed data loading period of the second data memory and the stored time difference is close to the reference time interval and the Kth previous data from the last in the second data memory is output as the corresponding data, and whereby when the specified data is in the second data memory, a value K is obtained which makes the sum of the value of addition of the successive data loading intervals stored in the first data loading interval memory during the time between the loading of the last data in the first data memory and the loading of the Kth previous data therefrom and the value of the stored time difference close to the reference time interval, and the Kth data from the last in the first data memory is output as the corresponding data.

Claim 6

A logic analyzer according to claim 2 wherein the corresponding data detecting means comprises reference time interval computing means for computing, as a reference time interval, the time interval between the loading of the specified data and the later one of the data load stop times of the first and second data memories, and means for obtaining, from one of the first and second data memories having not stored therein the specified data, data corresponding to the time difference between the data loading time and the said later data load stop time, which difference is close to the reference time interval.

Claim 7

A logic analyzer according to claim 5 wherein the corresponding data obtaining means is a means whereby when the specified data is in the first data memory and the first data memory is stopped from the data loading thereinto after the second data memory, a value K is determined so that the sum of a K-fold value of the data loading period of the second data memory and the stored time difference may become close to the reference time interval and Kth data from the last in the second data memory is output as the corresponding data, whereby when the specified data is in the first data memory and the second data memory is stopped from the data loading thereinto after the first data memory, a value K is determined so that a K-fold value of the data loading period of the second data memory may become close to the reference time interval and Kth data from the last in the second data memory is output as the corresponding data, whereby when the specified data is in the second data memory and the first data memory is stopped from the data loading thereinto after the second data memory, a value K is determined so that the sum value of the successive data loading intervals stored in the first data loading interval memory during the time between the loading of the Kth data from the last and the loading of the last data, may become close to the reference time interval and the Kth data from the last in the first data memory is output as the corresponding data, and whereby when the specified data is in the second data memory and the second data memory is stopped from the data loading thereinto after the first data memory, a value K is determined so that the sum of the value of addition of the successive data loading intervals stored in the first data loading interval memory during the time between the loading of the Kth data from the last and the loading of the last data, and the value of the stored time difference may become close to the reference time interval and the Kth data from the last in the first data memory is output as the corresponding data.

Claim 8

A logic analyzer according to claim 5 wherein the reference time interval computing means is a means whereby when the specified data is in the first data memory and the first data memory is stopped from the data loading thereinto after the second data memory, the successive data loading intervals stored in the first data loading interval memory during the time between the loading of the last data into the first data memory and the loading of the specified data, are added together to obtain the reference time interval, whereby when the specified data is in the first data memory and the second data memory is stopped from the data loading thereinto after the first data memory, the sum of the successive data loading intervals stored in the first data loading interval memory during the time between the loading of the last data into the first data memory and the loading of the specified data thereinto, and the stored time difference to obtain the reference time interval, whereby when the specified data is in the second data memory and the first data memory is stopped from the data loading thereinto after the second data memory, the number of data inputs into the second data memory during the time between the loading of the specified data and the stopping of the data loading into the second data memory and its data loading period are multiplied and the multiplied value is added to the stored time difference to obtain the reference time interval, and whereby when the specified data is in the second data memory and the second data memory is stopped from the data loading thereinto after the first data loading, the number of data inputs into the second data memory during the time between the loading of the specified data and the stopping of the data loading into the second data memory and its data loading period are multiplied to obtain the reference time interval.

Claim 9

A logic analyzer according to claim 1 wherein the second input data is loaded for each change in state thereof, which further comprises a second data loading interval measuring circuit for measuring the intervals of loading of the second input data and a second data loading interval memory for storing the data loading intervals measured by the second data loading interval measuring circuit, and wherein the data loading intervals stored in the second data loading interval memory are also used for obtaining the corresponding data by the corresponding data detecting means.

Claim 10

A logic analyzer according to claim 8 wherein the corresponding data detecting means comprises reference time interval computing means for computing, as a reference time interval, the time interval between the loading of the data specified by the specifying means and the stopping of the data loading into one of the first and second data memories having stored therein the specified data, and means whereby the time interval between the stopping of the data loading into the other data memory and each data loading thereinto and the time difference stored in the time difference memory are added including its sign to obtain data corresponding to that one of the added values which is close to the reference time interval.

Claim 11

A logic analyzer according to claim 9 wherein the reference time interval computing means is a means whereby when the specified data is in the first data memory, the successive data loading intervals stored in the first data loading interval memory during the time between the loading bf the specified data and the stopping of data loading into the first data memory, are added together to obtain the reference time interval, and whereby when the specified data is in the second data memory, the successive data loading intervals stored in the second data loading interval memory during the time between the loading of the specified data and the stopping of data loading into the second data memory, are added together to obtain the reference time interval, and wherein the corresponding data obtaining means is a means whereby when the specified data is in the first data memory, a value K is determined so that the sum of the value of addition of the intervals of the successive data loading intervals stored in the second data loading interval memory during the time between the loading of the last data in the second data memory and the loading of the Kth previous data therefrom and the stored time difference may become close to the reference time interval, and the Kth data from the last in the second data memory is output as the corresponding data, and whereby when the specified data is in the second data memory, a value K is determined so that the sum of the value of addition of the intervals of the successive data loading intervals stored in the first data loading interval memory during the time between the loading of the last data in the first data memory and the loading of the Kth previous data therefrom and the stored time difference may become close to the reference time interval, and the Kth data from the last in the first data memory is output as the corresponding data.

Claim 12

A logic analyzer according to claim 8 wherein the corresponding data detecting means comprises reference time interval computing means for computing, as a reference time interval, the time between the loading of the specified data and the stopping of the data loading into one of the first and second data memories which is stopped from the data loading thereinto after the other, and means for obtaining, from that one of the first and second data memories having not stored therein the specified data, data corresponding to the time difference between the data loading time and the said later data load stop time, which difference is close to the reference time interval.

Claim 13

A logic analyzer according to claim 11 wherein the reference time interval computing means is a means whereby when that one of the first and second data memories having stored therein the specified data is stopped from data loading thereinto after the other data memory, the data loading intervals stored in the data loading interval memory corresponding to the said one data memory during the time between the loading of the specified data and the stopping of data loading, are added together to obtain the reference time interval, and whereby when the data memory having stored therein the specified data is stopped from data loading thereinto before the other data memory is stopped the successive data loading intervals within the time between the loading of the specified data and the stopping of the data loading, stored in the data loading interval memory corresponding to the data memory having stored therein the specified data, and the stored time difference are added together to obtain the reference time interval, and wherein the corresponding data obtaining means is a means whereby when one of the first and second data memories having stored therein the specified data is stopped from data loading thereinto after the other data memory, a value K is determined so that the sum of the value of addition of the successive data loading intervals stored in the data loading interval memory corresponding to the said other data memory during the time between the stopping of data loading into the said other data memory and the loading of the Kth data from the last therein and the stored time difference may become close to the reference time interval, and the Kth data from the last in the data memory having not stored therein the specified data is output as the corresponding data, and whereby when the data memory having stored therein is stopped from data loading thereinto before the other data memory, a value K is determined so that the value of addition of the successive data loading intervals stored in the data loading interval memory corresponding to the said other data memory during the time between the stopping of the data loading into the said other data memory and the loading of the Kth data from the last therein may become close to the reference time interval, and the Kth data from the last in the data memory having not stored therein the specified data is output as the corresponding data.

Claim 14

A logic analyzer according to claim 1 wherein the loading of the second input data into the second data memory is effected by means for loading the second input data with a fixed period, means for loading the second input data for each change in state thereof and means for switching the both loading means, which comprises a second data loading interval measuring circuit for measuring the intervals of loading of the second input data and a second data loading interval memory for storing the data loading intervals measured by the second data loading interval measuring circuit, and wherein the corresponding data detecting means obtains the corresponding data also utilizing the data loading intervals stored in the second data loading interval memory.

Claim 15

A logic analyzer according to claim 1, 2, 8 of 13 further including trigger priority means for giving priority to only one of the first and second trigger detectors to make it operative, the other trigger detector being made operative by the output of the priority-given trigger detector.

Claim 16

A logic analyzer according to claim 1, 2, 8 or 13, further comprising first display means for displaying data transferred from the first data memory, first transfer means for transferring data from the first data memory to the first display means, first cursor control means capable of indicating the data displayed on the display means by a first cursor and changing the position of indication by the first cursor, second display means for display data transferred from the second data memory, second transfer means for transferring the data from the second data memory to the second display means, second cursor control means capable of indicating the data displayed on the display means by a second cursor and changing the position of indication by the second cursor, and cursor interconnecting means whereby when the position of indication by one of the first and second cursors is changed, data at the new position is obtained, as the specified data, by the corresponding data detecting means, and the other cursor is caused to indicate the corresponding data.

Claim 17

A logic analyzer according to claim 15 further comprising means which when the data to be indicated by the other cursor under control of the cursor interconnecting means is not present in the display means which is to display the data, includes means for rendering the corresponding data transfer means to transfer the data from the corresponding data memory to the corresponding display means.

Claim 18

A logic analyzer according to claim 1, 2, 8 or 13 further comprising first display means for displaying data transferred from the first data memory, first transfer means for transferring the data from the first data memory to the first display means, second display means for displaying data transferred from the second data memory, second transfer means for transferring the data from the second data memory to the second display means, scroll means for driving the first or second transfer means to update and display data on the first or second display means, and scroll associating means which obtains the corresponding data in the second or first data memory by the corresponding data detecting means using, as the specified data, data at a predetermined position on the display screen of the first or second display means and drives the second or first transfer means so that the corresponding data is displayed at a predetermined position on the second or first display means.

Claim 19

A logic analyzer according to claim 17 for indicating the predetermined position on the display screen of the first display means by the first cursor and capable of changing the predetermined position by changing the position of indication by the first cursor, and second cursor control means for indicating the predetermined position on the display screen of the second display means by the second cursor and capable of changing the predetermined position by changing the position of indication by the second cursor.