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Patent EP0181011A2 successfully refreshed from Google Patents.
EP0181011A2
Expired / Lapsed
EP
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A method and circuit detecting the logic state of internal nodes in sequential logic circuits
Assignee: Monolithic Memories Inc
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Filing: 1985-05-25
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Granted: —
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Expires: 2005-05-25
Abstract
Abstract A circuit is provided which overrides the normal output signal of a sequential logic circuit, and provides an output signal indicative of the logical state of an internal node which is normally accessible via the output terminals of the sequential logic circuit. These output signals are provided to faciliate adequate testing of the sequential logic circuit in a minimum of time.
Inventors
- 👤 Robert J. Bosnyak
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 17:57
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
71 words
The method for testing sequential logic circuits including at least one register, comprising the steps of: monitoring the input signals to said sequential logic circuit; providing output signals indicative of internal states of said sequential logic circuit without disturbing the contents of said at least one register; and comparing said output signals to the expected output signal of said sequential logic circuit which are expected in response to said input signals.
Claim 2
Independent Claim
71 words
The method for testing sequential logic circuits including at least one register, comprising the steps of: monitoring the input signals to said sequential logic circuit; providing output signals indicative of internal states of said sequential logic circuit without disturbing the contents of said at least one register; and comparing said output signals to the expected output signal of said sequential logic circuit which are expected in response to said input signals.
Claim 3
Dependent Claim
213 words
An output buffer circuit for a sequential logic circuit having a first input terminal, a second input terminal, a test input terminal, and an output terminal, comprising: first data transfer means having an input lead connected to said first input terminal, an output lead connected to said output terminal, and a control input lead connected to said test input lead, wherein when a first signal is provided on said control input lead, said first data transfer means provides on said output terminal a signal related to the input signal provided on said input lead, and wherein when a second signal is provided on said control input lead said first data transfer means provides a high impedance on said output terminal; and second data transfer means having an input lead connected to said second input terminal, an output lead connected to said output terminal, and a control input terminal connected to said test input terminal, wherein when said first signal is provided on said control input lead, said second data transfer means provides a high impedance on said output terminal, and wherein when said second signal is provided on said control lead said second data transfer means provides on said output terminal a signal related to the input signal provided on said input lead.
Claim 4
Dependent Claim
213 words
An output buffer circuit for a sequential logic circuit having a first input terminal, a second input terminal, a test input terminal, and an output terminal, comprising: first data transfer means having an input lead connected to said first input terminal, an output lead connected to said output terminal, and a control input lead connected to said test input lead, wherein when a first signal is provided on said control input lead, said first data transfer means provides on said output terminal a signal related to the input signal provided on said input lead, and wherein when a second signal is provided on said control input lead said first data transfer means provides a high impedance on said output terminal; and second data transfer means having an input lead connected to said second input terminal, an output lead connected to said output terminal, and a control input terminal connected to said test input terminal, wherein when said first signal is provided on said control input lead, said second data transfer means provides a high impedance on said output terminal, and wherein when said second signal is provided on said control lead said second data transfer means provides on said output terminal a signal related to the input signal provided on said input lead.
Claim 5
Dependent Claim
248 words
An output buffer circuit for a sequential logic circuit having a first input terminal, a plurality of K second input terminals, where K is a positive integer, a test input terminal, an input select port, and an output terminal, comprising: first data transfer means having an input lead connected to said first input terminal, an output lead connected to said output terminal, and a control input lead connected to said test input lead, wherein when a first signal is provided on said control input lead said first data transfer means provides on said output lead a signal related to the imput signal provided on said first input terminal, and wherein when a second signal is provided on said control input lead said first data transfer means provides a high impedance on said output terminal; and second data transfer means having K input leads, each uniquely connected to one of said input terminals, an output lead connected to said output terminal, and a control input lead connected to said test input terminal, wherein when said first signal is provided on said control input lead said second data transfer means provides a high impedance on said output terminal and wherein when said second signal is provided on said control input lead said second data transfer means provides on said output terminal a signal related to a selected one of said K input signals provided on said K input terminals selected in response to signals provided on said input select port.
Claim 6
Dependent Claim
248 words
An output buffer circuit for a sequential logic circuit having a first input terminal, a plurality of K second input terminals, where K is a positive integer, a test input terminal, an input select port, and an output terminal, comprising: first data transfer means having an input lead connected to said first input terminal, an output lead connected to said output terminal, and a control input lead connected to said test input lead, wherein when a first signal is provided on said control input lead said first data transfer means provides on said output lead a signal related to the imput signal provided on said first input terminal, and wherein when a second signal is provided on said control input lead said first data transfer means provides a high impedance on said output terminal; and second data transfer means having K input leads, each uniquely connected to one of said input terminals, an output lead connected to said output terminal, and a control input lead connected to said test input terminal, wherein when said first signal is provided on said control input lead said second data transfer means provides a high impedance on said output terminal and wherein when said second signal is provided on said control input lead said second data transfer means provides on said output terminal a signal related to a selected one of said K input signals provided on said K input terminals selected in response to signals provided on said input select port.
References Cited (Backward Citations)
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