Bipolar-transistor type random access memory device having a redundancy configuration

Claim 2

A bipolar-transistor type random access memory device, characterised by a memory cell array (1) including a plurality of memory cells; a redundancy memory cell array (7) including a plurality of memory cells; means (2) for receiving an address signal (W-ADD); means (14,3), operatively connected to the address receiving means, for selecting a normal memory cell in the memory cell array in response to the address signal from the address receiving means; means (9) for storing one or more defective memory addresses (DW-ADD) of one or more defective memory cells in the memory cell array; means (10), operatively connected to the defective address storing means, for receiving the address signal independently of the address receiving means and one or more defective memory address signals from the defective address storing means and for comparing the address signal with the defective memory address signals; and means (8), operatively connected to the address receiving and comparing means, for selecting a memory cell in the redundancy memory cell array corresponding to a defective memory cell in the memory cell array, the normal memory cell selecting means (14,3) being energised when the address signal does not equal the defective memory address signal, the redundancy memory cell selecting means (8) being energised otherwise.

Claim 3

A device according to claim 1, characterised in that each memory cell in the redundancy memory cell array (7) has a circuit configuration the same as each memory cell in the memory cell array (1).

Claim 4

A device according to claim 2, characterised in that the defective address storing means (9) includes a programable read-only-memory (PROM) for storing said one or more defective memory address signals and for outputting those address signals to the address receiving and comparing means (10).

Claim 7

An emitter-coupled-logic type random access memory device, characterised by a memory cell array (1) including a plurality of memory cells, each memory cell comprising an emitter-coupled-logic (ECL) flip-flop; a redundancy memory cell array (7) including a plurality of memory cells, each memory cell comprising an ECL flip-flop; means (2) for receiving an address signal (W-ADD) and formed by ECL circuits; means (14,3), operatively connected to the address receiving means, for selecting a normal memory cell in the memory cell array in response to the address signal from the address receiving means, and comprising ECL circuits; means (9) for storing one or more defective memory addresses (DW-ADD) of one or more defective memory cells in the memory cell array; means (10), operatively connected to the defective address storing means, for receiving the address signal independently of the address receiving means and one or more defective memory address signals from the defective address storing means and for comparing the address signal with the defective memory address signals, and comprising ECL circuits; and means (8), operatively connected to the address receiving and comparing means, for selecting a memory cell in the redundancy memory cell array corresponding to a defective memory cell in the memory cell array, and comprising ECL circuits, the normal memory cell selecting means (14,3), being energised when the address signal does not equal the defective memory address signal, the redundancy memory cell selecting means (8) being energised otherwise.

Claim 8

An emitter-coupled-logic type random access memory device, characterised by a memory cell array (1) including a plurality of memory cells, each memory cell comprising an emitter-coupled-logic (ECL) flip-flop; a redundancy memory cell array (7) including a plurality of memory cells, each memory cell comprising an ECL flip-flop; means (2) for receiving an address signal (W-ADD) and formed by ECL circuits; means (14,3), operatively connected to the address receiving means, for selecting a normal memory cell in the memory cell array in response to the address signal from the address receiving means, and comprising ECL circuits; means (9) for storing one or more defective memory addresses (DW-ADD) of one or more defective memory cells in the memory cell array; means (10), operatively connected to the defective address storing means, for receiving the address signal independently of the address receiving means and one or more defective memory address signals from the defective address storing means and for comparing the address signal with the defective memory address signals, and comprising ECL circuits; and means (8), operatively connected to the address receiving and comparing means, for selecting a memory cell in the redundancy memory cell array corresponding to a defective memory cell in the memory cell array, and comprising ECL circuits, the normal memory cell selecting means (14,3), being energised when the address signal does not equal the defective memory address signal, the redundancy memory cell selecting means (8) being energised otherwise.

Claim 9

A device according to claim 6, characterised in that each memory cell in the redundancy memory cell array (7) has a circuit configuration the same as each memory cell in the memory cell array (1).

Claim 10

A device according to claim 7, characterised in that the defective address storing means (9) includes a programable read-only-memory (PROM) for storing said one or more defective memory address signals and for outputting those address signals to the address receiving and comparing means.

Claim 13

A device according to claim 10, characterised by an emitter follower circuit (20) for receiving and level-shifting the address signal (W-ADD); wherein the address receiving means (2'), operatively connected to the emitter follower circuit, includes a plurality of current switch circuits (2b) connected in parallel, each being operable in response to the level-shifted address signal from the emitter follower circuit; wherein the normal memory cell selecting means (14,3) includes a decoder energising circuit (14a) including a plurality of transistors (Q11) connected in parallel, each being operable in response to an output of the corresponding current switch circuit in the address receiving means, for energising an address decoding circuit (14b); a gate circuit including a plurality of gates connected in parallel, each having a transistor (Q 7 ) operable in response to an output (SR) from the address receiving and comparing means and one or more transistors (Q5, Q 6 ) connected in parallel with each other and the transistor (Q 7 ) and operable in response to one or more outputs from the address decoding circuit, and a driver circuit including a plurality of transistors (Q 8 ) connected in parallel, each driving a corresponding address line (WL) in said memory cell array; wherein the address receiving and comparing means (10'), operatively connected to the emitter follower circuit (20), includes a plurality of compare circuits (lOb), each having a plurality of transistors (Q 13 , Q 141 Q 15' Q 16 ) for each address bit of the address signal, for comparing the address signal from the emitter follower circuit with the defective memory address signals from the defective address storing means, and a plurality of gate circuits (10c), each having two transistors (Q 17 , Q 18 ) connected in parallel; and wherein the redundancy memory cell selecting means (8) includes a gate circuit having a transistor (Q 19 ) operable in response to the output (SR) from the address receiving and comparing means and a transistor (Q20) connected in parallel with the transistor (Q 19 ) and receiving a base voltage between the low and high of the output from the address receiving and comparing means; and a driver circuit including a transistor (Q 21 ) for driving a redundancy address line (WL(R)) in the redundancy memory cell array.

Claim 14

A device according to claim 10, characterised in that the address receiving means (2) includes an emitter follower circuit (2a) for receiving and level-shifting the address signal (W-ADD), a plurality of current switch circuits (2b) connected in parallel, each being operable in response to the level-shifted address signal from the emitter follower circuit; in that the normal memory cell selecting means (14,3) includes a decoder energising circuit (14a) including a plurality of transistors (Q11) connected in parallel, each being operable in response to an output of the corresponding current switch circuit in the address receiving means, for energising an address decoding circuit (14b), a gate circuit including a plurality of gates connected in parallel, each having a transistor (Q 7 ) operable in response to an output (SR) from the address receiving and comparing means and one or more transistors (Q 5 , Q 6 ) connected in parallel with each other and said transistor (Q 7 ) and operable in response to one or more outputs from the address decoding circuit, and a driver circuit including a plurality of transistors (Q 8 ) connected in parallel, each driving a corresponding address line (WL) in the memory cell array; in that the address receiving and comparing means (10) includers an emitter follower circuit (10a) for receiving and level-shifting the address signal (W-ADD), a plurality of compare circuits (10b), each having a plurality of transistors (Q13. Q 14' Q 15' Q 16 ) for each address bit of the address signal, for comparing the address signal from the emitter follower circuit with the defective memory address signals from the defective address storing means, and a plurality of gate circuits (10c), each having two transistors (Q 17 , Q 18 ) connected in parallel; and in that the redundancy memory cell selecting means (8) includes a gate circuit having a transistor (Q 19 ) operable in response to the output (SR) from the address receiving and comparing means and a transistor (Q 20 ) connected in parallel to the transistor (Q 19 ) for receiving a base voltage between the low and high of the output from the address receiving and comparing means, and a driver circuit including a transistor (Q 21 ) for driving a redundancy address line (WL(R)) in the redundancy memory cell array.