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EP0178949A2
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Bipolar-transistor type semiconductor memory device having a redundancy configuration
Assignee: Fujitsu Ltd
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Filing: 1985-10-18
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Granted: —
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Expires: 2005-10-18
Abstract
Abstract A bipolar-transistor type semiconductor memory device includes a memory cell array (1), a redundancy memory cell array (10), a redundancy driving circuit (11), and a redundancy address decision circuit (12,13). The redundancy driving circuit includes an emitter-coupled logic gate (Q20,Q21,R8,IS14) which compares the voltage level of an input signal with a reference voltage level to produce an enabling signal for the redundancy memory cell array. When the redundancy address decision circuit judges that the input address coincides with the address of a defective circuit portion of the memory device, the redundancy driving circuit operates to enable the redundancy memory cell array instead of the normal memory cell array.
Inventors
- 👤 Tomoharu Awaya
- 👤 Isao Fukushi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 14:19
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C29/00; G11C29/70; G11C29/78; G11C29/84; G11C29/842
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
160 words
A bipolar-transistor type semiconductor memory device having a redundancy configuration, characterised by a memory cell array (1); a redundancy memory cell array (10); a driving circuit (2) including an emitter-coupled logic gate (Q1,Q2,R1,IS1) for comparing a voltage level of an input signal with a voltage level of a reference signal to enable the memory cell array; a redundancy driving circuit (11) including an emitter-coupled logic gate (Q20,Q21,R8,IS14) for comparing a voltage level of an input signal with a voltage level of a reference signal to enable the redundancy memory cell array; and a redundancy address decision circuit (12,13) for deciding whether an input address coincides with an address of a defective circuit portion and for outputting a switching signal (SR) in accordance with results of the decision, the switching signal being applied to input signal input of the emitter-coupled logic gate of the redundancy driving circuit and a reference signal input of the emitter-coupled logic gate of the driving circuit.
Claim 2
Dependent Claim
160 words
A bipolar-transistor type semiconductor memory device having a redundancy configuration, characterised by a memory cell array (1); a redundancy memory cell array (10); a driving circuit (2) including an emitter-coupled logic gate (Q1,Q2,R1,IS1) for comparing a voltage level of an input signal with a voltage level of a reference signal to enable the memory cell array; a redundancy driving circuit (11) including an emitter-coupled logic gate (Q20,Q21,R8,IS14) for comparing a voltage level of an input signal with a voltage level of a reference signal to enable the redundancy memory cell array; and a redundancy address decision circuit (12,13) for deciding whether an input address coincides with an address of a defective circuit portion and for outputting a switching signal (SR) in accordance with results of the decision, the switching signal being applied to input signal input of the emitter-coupled logic gate of the redundancy driving circuit and a reference signal input of the emitter-coupled logic gate of the driving circuit.
Claim 3
Dependent Claim
72 words
A device according to claim 1, characterised in that the high and low voltage levels of the switching signal from the redundancy address decision circuit (12,13) are shifted in comparison with the high and low voltage levels of the input signal of the driving circuit (2), and the voltage level of the reference signal of the redundancy driving circuit (11) is between the high and low voltage levels of the switching signal.
Claim 4
Dependent Claim
65 words
A device according to claim 2, characterised in that the high voltage level cf the switching signal (SR) from the redundancy address decision circuit (12,13) is between the high and low levels of the input signal of the driving circuit (2), and the low voltage level of the switching signal is lower than the low voltage level of the input signal of the driving circuit.
Claim 5
Independent Claim
51 words
A device according to any preceding claim, characterised in that the redundancy address decision circuit (12,13) comprises a memory circuit (12) for storing the address of the defective circuit portion, and a comparison gate (13) for comparing the input address with the content of the memory circuit to decide the coincidence.
Claim 6
Dependent Claim
17 words
A device according to claim 4, characterised in that the comparison gate (13) is an exclusive-OR circuit.
Claim 7
Dependent Claim
21 words
A device according to claim 4 or claim 5, characterised in that the memory circuit (12) is a programmable read-only memory.
Claim 8
Independent Claim
43 words
A device according to any preceding claim, characterised in that the driving circuit (2) and the redundancy driving circuit (11) comprise emitter-coupled logic gates (Ql,Q2; Q4,Q5; Q20,Q21) and a driving transistor (Q3,Q6,Q22) driven by the emitter-coupled logic gate to enable the memory cell.
Claim 9
Dependent Claim
153 words
A bipolar-transistor type semiconductor memory device having a redundancy configuration, characterised by a memory cell array (1); a redundancy memory cell array (10); a decoding circuit (3) for decoding an input address; a driving circuit (2) connected to the decoding circuit for enabling the memory cell array in accordance with the input address; a redundancy driving circuit (11) capable of enabling the redundancy memory cell array; a redundancy address decision circuit (12,14) for deciding whether the input address coincides with an address of a defective circuit portion and for outputting a switching signal (SR) in accordance with results of the decision; and a redundancy selection circuit (Q23) for placing all output signals of the decoding circuit in the non-selection state while driving the redundancy driving circuit to enable the redundancy memory cell array instead of the defective circuit portion on the basis of the switching signal output from the redundancy address decision circuit.
Claim 10
Dependent Claim
153 words
A bipolar-transistor type semiconductor memory device having a redundancy configuration, characterised by a memory cell array (1); a redundancy memory cell array (10); a decoding circuit (3) for decoding an input address; a driving circuit (2) connected to the decoding circuit for enabling the memory cell array in accordance with the input address; a redundancy driving circuit (11) capable of enabling the redundancy memory cell array; a redundancy address decision circuit (12,14) for deciding whether the input address coincides with an address of a defective circuit portion and for outputting a switching signal (SR) in accordance with results of the decision; and a redundancy selection circuit (Q23) for placing all output signals of the decoding circuit in the non-selection state while driving the redundancy driving circuit to enable the redundancy memory cell array instead of the defective circuit portion on the basis of the switching signal output from the redundancy address decision circuit.
Claim 11
Dependent Claim
49 words
A device according to claim 8, characterised in that the redundancy address decision circuit comprises a memory circuit (12) for storing the address of the defective circuit portion, and a comparison gate (14) for comparing the input address with the content of the memory circuit to decide the coincidence.
Claim 12
Dependent Claim
17 words
A device according to claim 9, characterised in that the comparison gate (14) is an exclusive-NOR circuit.
Claim 13
Dependent Claim
18 words
A device according to claim 9, characterised in that the memory circuit (12) is a programmable read-only memory.
Claim 14
Independent Claim
39 words
A device according to any one of claims 8-11, characterised in that the decoding circuit (3) comprises an address buffer circuit (4) and decoder lines (5) to which the output lines of the address buffer circuit are suitably connected.
Claim 15
Independent Claim
57 words
A device according to any one of claims 8-12, characterised in that the redundancy selection circuit comprises a multiemitter transistor (Q23) driven by the switching signal (SR) from the redundancy address decision circuit (12,14), the emitters of the multiemitter transistor being connected to the decoder lines (5) and the input of the redundancy driving circuit (11), respectively.
Claim 16
Independent Claim
42 words
A device according to any one of claims 8-13, characterised in that the driving circuit (2) and the redundancy driving circuit (11) comprise an emitter-coupled logic gate and a driving transistor driven by the emitter-coupled logic gate to enable the memory cell.
Claim 17
Independent Claim
27 words
A device according to any one of claims 8-14, characterised in that the driving circuit (2) and the redundancy driving circuit (11) are constituted by diode matrixes.
References Cited (Backward Citations)
No citation records indexed.
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