Bipolar-transistor random access memory having a redundancy configuration

Claim 2

A semiconductor memory device of a bipolar-transistor type comprising; a memory cell array (1); a redundancy memory cell array (2); means for receiving an address signal (A 0 ~, A 7 ); means (3, 4, 5) for selecting a normal memory cell from said memory cell array in accordance with said address signal (A 0 ~ A7) from said address receiving means; means (6) for storing a defective address of a defective memory cell of said memory cell array, said defective address storing means comprising a plurality of 1-bit memory circuits (6-0, 6-1, ..., 6-7) of a diode type, each circuit corresponding to each bit of said defective address (A 0R ~ A 7R ); and means (7) for comparing the address of said address signal (A 0 ~ A 7 ) from said address receiving means with said defective address (A 0R ~ A 7R ) of said defective address storing means (6) so as to disable said normal memory cell selecting means (3, 4, 5) and select said redundancy memory cell array (2) when the address of said address signal (A 0 ~ A 7 ) is different from said defective address (A 0R ~ A 7R ).

Claim 3

A device as set forth in claim 1, wherein each of 1-bit memory circuits (6-0 ~ 6-7) comprises; a first power supply means (V CC ); a second power supply means (VEE); a write power supply means (V P ); a node (N 1 ); at least three diode stages (D 1 ~ D 3 ) linked along a forward bias direction between said first power supply means (V CC ) and said node (N 1 ); a current source (IS) or resistor linked between said node (N 1 ) and said second power supply means (VEE); a diode stage (D 0 ) linked along a backward bias direction between said write power supply means (Vp) and said first power supply means (VCC); a short-circuited junction type PROM cell (PC) linked between said write power supply means (V P ) and said node (N 1 ); and - a switching element (Q 1 ), linked between said node (N 1 ) and said second power supply means (VEE), for receiving one bit of said address signal (A0 ~ A 7 ), whereby generating a high or low potential from said node (N 1 ) in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 4

A device as set forth in claim 1, wherein each of 1-bit memory circuits (6-0 ~ 6-7) comprises; a first power supply means (V CC ); a second power supply means (VEE); a write power supply means (Vp); a node (N 1 ) ; at least two diode stage (D 1 , D 2 ) linked along a forward bias direction between said first power supply means (V CC ) and said node (N 1 ); a current source (IS) or resistor linked between said node (N 1 ) and said second power supply means (VEE); a resistor (R 0 ) linked between said write power supply means (Vp) and said first power supply means (VCC); a short-circuited junction type PROM cell (PC) linked between said write power supply means (Vp) and said node (N 1 ); and a switching element (Q 1 ), linked between said node (N 1 ) and said second power supply means (V EE ), for receiving one bit of said address signal (A 0 ~ A 7 ), whereby generating a high or low potential from said node (N 1 ) in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 5

A device as set forth in claim 1, wherein each of 1-bit memory circuits (6-0 ~ 6-7) comprises; a first power supply means (V CC ); a second power supply means (VEE); a write power supply means (V P ); first and second nodes (N 0 , N 1 ); a diode stage (D 0 ) linked along a forward bias direction between said first power supply means (V CC ) and said first node (N D ); a least two diode stages (D 1 , D 2 ) linked along a forward bias direction between said first node (N 0 ) and said second node (N 1 ); a current source (IS) or resistor linked between said second node (N 1 ) and said second power supply means (VEE); a short-circuited junction type PROM cell (PC) linked between said write power supply means (V P ) and said second node (N 1 ); and a switching element (Q 1 ), linked between said second node (N 1 ) and said second power supply means (VEE), for receiving one bit of said address signal (A 0 ~ A 7 ), whereby generating a high or low potential from said node (N 1 ) in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 6

A device as set forth in claim 1, wherein each of said 1-bit memory circuits (6-0~ 6-7) comprises; a first power supply means ( V CC ); a second power supply means (VEE); a write power supply means (V P ); first and second nodes (N 1 , N 2 ); at least three diode stages (D 1 ~D 3 ) along a forward bias direction between said first power supply means (V CC ) and said first node (N 1 ); a first resistor (R 1 ) linked between said first node (N 1 ) and said second power supply means (VEE); a diode stage (D 4 ) linked between said first and second nodes (N 1 , N 2 ), and having the same conduction direction as said at least three diode stages (D 1 ~D 3 ); a second resistor (R 2 ) linked between said second node (N 2 ) and said second power supply means (VEE); a diode stage (D 0 ) linked along a backward bias direction linked between said first power supply means (V CC ) and said write power supply means (V P ) ; a short-circuited junction type PROM cell (PC) linked between said write power supply means (Vp) and said second node (N 2 ); a switching element (Q 1 ), linked between said second node (N 2 ) and said second power supply means (VEE), for receiving one bit of said address signal (A 0 ~A 7 ); and output means (Q 2 ~Q 4 , R 3 ), connected to said first and second nodes (N 1 , N2), for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 7

A device as set forth in claim 1, wherein each of said 1-bit memory circuits (6-0~6-7) comprises; a first power supply means (V CC ); a second power supply means (VEE); a write power supply means (Vp); first and second nodes (N 1 , N 2 ); at least three diode stages (D 1 ~D 3 ) along a forward bias direction between said first power supply means (V CC ) and said first node (N 1 ); a first resistor (R 1 ) linked between said first node (N 1 ) and said second power supply means (VEE); at least four diode stages (D 1 '~D 3 ', D 4 ) linked along a forward bias direction between said first power supply means (V CC ) and said second node (N 2 ); a second resistor (R 2 ) linked between said second node (N 2 ) and said second power supply means (VEE); a diode stage (D 0 ) linked along a backward bias direction linked between said first power supply means (V CC ) and said write power supply means (Vp); and a short-circuited-junction type PROM cell (PC) linked between said write power supply means (Vp) and said second node (N 2 ); a switching element (Q 1 ), linked between said second node (N 2 ) and said second power supply means (V EE ), for receiving one bit of said address signal (A 0 ~A 7 ); and output means (Q 2 ~Q 4 , R 3 ), connected to said first and second nodes (N 1 , N 2 ), for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 8

A device as set forth in claim 1, wherein each of said 1-bit memory circuits (6-0~6-7) comprises; a first power supply means (V CC ); a second power supply means (VEE); a write power supply means (Vp); first and second nodes (N 1 , N 2 ); at least two diode stages (D 1 , D 2 ) along a forward bias direction between said first power supply means (V CC ) and said first node (N 1 ); a first resistor (R 1 ) linked between said first node (N 1 ) and said second power supply means (VEE); a diode stage (D 4 ) linked between said first and second nodes (N 1 , N2), and having the same conduction direction as said at least two diode stages (D 1 , D 2 ); a second resistor (R 2 ) linked between said second node (N 2 ) and said second power supply means (VEE); a resistor (R 0 ) linked between said first power supply means (V CC ) and said write power supply means (V P ); a short-circuited-junction type PROM cell (PC) linked between said write power supply means (Vp) and said second node (N 2 ); a switching element (Q 1 ), linked between said second node (N 2 ) and said second power supply means (VEE), for receiving one bit of said address signal (A 0 ~A 7 ); and~ output means (Q 2 ~Q 4 , R 3 ), connected to said first and second nodes (N 1 , N 2 ), for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 9

A device as set forth in claim 1, wherein each of said 1-bit memory circuits (6-0~6-7) comprises; a first power supply means (V CC ); a second power supply means (V EE ); a write power supply means (V P ); first, second, and third nodes (N 0 , N 1 , N2); a diode stage (D 0 ) linked along a forward bias direction between said first power supply means (V CC ) and said first node (N 0 ); at least two diode stages (D 1 , D 2 ) along a forward bias direction between said first and second nodes (N 0 , N 1 ); a first resistor (R 1 ) linked between said second node (N 1 ) and said second power supply means (VEE); a diode stage (D 4 ) linked between said first and second nodes (N 1 , N2), and having the same conduction direction as said at least two diode stages (D 1 , D 2 ); a second resistor (R 2 ) linked between said second node (N 2 ) and said second power supply means (VEE); a short-circuited junction type PROM cell (PC) linked between said write power supply means (Vp) and said third node (N2); a switching element (Q 1 ), linked between said third node (N 2 ) and said second power supply means (VEE), for receiving one bit of said address signal (A 0 ~A7); and output means (Q 2 ~Q 4 , R3), connected to said second and third nodes (N 1 , N2), for detecting the difference in potential in accordance with the short-circuited or mon-short-circuited state of said PROM cell (PC).

Claim 10

A device as set forth in claim 1, wherein each of said 1-bit memory circuits (6-0~6-7) comprises; a first power supply means (VCC); a second power supply means (V EE ); a write power supply means (Vp); first and second nodes (N 1 , N 2 ); at least two diode stages (D 1 , D 2 ) along a forward bias direction between said first power supply means (V CC ) and said first node (N 1 ); a first resistor (R 1 ) linked between said first node (N 1 ) and said second power supply means (V EE ); at least three diode stages (D 1 ', D 2 ', D 4 ) linked along a forward bias direction between said first power supply means (V CC ) and said second node (N2); a second resistor (R 2 ) linked between said second node (N 2 ) and said second power supply means (V EE ); a diode stage (DO) linked along a backward bias direction linked between said first power supply means (V CC ) and said write power supply means (V P ); a short-circuited junction type PROM cell (PC) linked between said write power supply means (Vp) and said second node (N 2 ); a switching element (Q 1 ), linked between said second node (N 2 ) and said second power supply means (VEE), for receiving one bit of said address signal (A 0 ~A 7 ); and output means (Q 2 ~Q 4 , R 3 ), connected to said first and second nodes (N 1 , N2), for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 11

A device as set forth in claim 1, further comprising means, linked between said address receiving means, linked between said address receiving means and said defective address storing means, for transmitting said address signal (A 0 ~A7) to said defective address storing means during a defective address writinc mode and allowing no transmission of said address signal (A 0 ~A 7 ) to said defective address storing means.

Claim 12

A device as set forth in claim 10, wherein said switching means comprises level shift means for reducing the output amplitude of said address receiving means so that the input amplitude of said defective address storing means is smaller than the output amplitude of said defective address storing means.

Claim 13

A device as set forth in claim 11, wherein said level shift means comprises one or more stages of emitter followers, diodes, or resistors.

Claim 14

An information memory device comprising: a first power supply means (V CC ) ; a second power supply means (VEE); a write power supply means (V P ); a node (N 1 ); at least three diode stages (D 1 ~D3) linked along a forward bias direction between said first power supply means (V CC ) and said node (N 1 ); a current source (I S ) or resistor linked between said node (N 1 ) and said second power supply means (VEE); a diode stage (D 0 ) linked along a backward bias direction between said write power supply means (V P ) and said first power supply means (V CC ); a short-circuited-junction type PROM cell (PC) linked between said write power supply means (V P ) and said node (N 1 ); and a switching element (Q 1 ), linked between said node (N 1 ) and said second power supply means (VEE); whereby generating a high or low potential from said node (N 1 ) in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 15

An information memory device comprising: a first power supply means (V CC ) ; a second power supply means (VEE); a write power supply means (V P ); a node (N 1 ); at least three diode stages (D 1 ~D3) linked along a forward bias direction between said first power supply means (V CC ) and said node (N 1 ); a current source (I S ) or resistor linked between said node (N 1 ) and said second power supply means (VEE); a diode stage (D 0 ) linked along a backward bias direction between said write power supply means (V P ) and said first power supply means (V CC ); a short-circuited-junction type PROM cell (PC) linked between said write power supply means (V P ) and said node (N 1 ); and a switching element (Q 1 ), linked between said node (N 1 ) and said second power supply means (VEE); whereby generating a high or low potential from said node (N 1 ) in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 16

An information memory device comprising: a first power supply means (V CC ); a second power supply means (VEE); a write power supply means (V P ); a node (N 1 ) ; at least two diode stages (D 1 , D 2 ) linked along a forward bias direction between said first power supply means (V CC ) and said node (N 1 ); a current source (IS) or resistor linked between said node (N 1 ) and said second power supply means (VEE); a resistor (R 0 ) linked between said write power supply means (Vp) and said first power supply means ( V cc); a short-circuited-junction type PROM cell (PC) linked between said write power supply means (V P ) and said node (N 1 ); and a switching element (Q 1 )' linked between said node (N 1 ) and said second power supply means (VEE); whereby generating a high or low potential from said node (N 1 ) in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 17

An information memory device comprising: a first power supply means (V CC ); a second power supply means (VEE); a write power supply means (V P ); a node (N 1 ) ; at least two diode stages (D 1 , D 2 ) linked along a forward bias direction between said first power supply means (V CC ) and said node (N 1 ); a current source (IS) or resistor linked between said node (N 1 ) and said second power supply means (VEE); a resistor (R 0 ) linked between said write power supply means (Vp) and said first power supply means ( V cc); a short-circuited-junction type PROM cell (PC) linked between said write power supply means (V P ) and said node (N 1 ); and a switching element (Q 1 )' linked between said node (N 1 ) and said second power supply means (VEE); whereby generating a high or low potential from said node (N 1 ) in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 18

An information memory device comprising: a first power supply means ( V CC ); a second power supply means (V EE ); a write power supply means (Vp); first and second nodes (N 0 , N l ); a diode stage (D 0 ) linked along a forward bias direction between said first power supply means (V CC ) and said first node (N 0 ) ; at least two diode stages (D 1 , D Z ) linked along a forward bias direction between said first node (N 0 ) and said second node (N 1 ); a current source (IS) or resistor linked between said second node (N 1 ) and said second power supply means (V EE ); a short-circuited junction type PROM cell (PC) linked between said write power supply means (Vp) and said second node (N 1 ) ; and a switching element (Q 1 ), linked between said second node (N 1 ) and said second power supply means (VEE); whereby generating a high or low potential from said node (N 1 ) in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 19

An information memory device comprising: a first power supply means ( V CC ); a second power supply means (V EE ); a write power supply means (Vp); first and second nodes (N 0 , N l ); a diode stage (D 0 ) linked along a forward bias direction between said first power supply means (V CC ) and said first node (N 0 ) ; at least two diode stages (D 1 , D Z ) linked along a forward bias direction between said first node (N 0 ) and said second node (N 1 ); a current source (IS) or resistor linked between said second node (N 1 ) and said second power supply means (V EE ); a short-circuited junction type PROM cell (PC) linked between said write power supply means (Vp) and said second node (N 1 ) ; and a switching element (Q 1 ), linked between said second node (N 1 ) and said second power supply means (VEE); whereby generating a high or low potential from said node (N 1 ) in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 20

An information memory device comprising: a first power supply means (V CC ); a second power supply means (V EE ); a write power supply means (Vp); first and second nodes (N 1 , N2); at least three diode stages (D 1 ~D3) along a forward bias direction between said first power supply means (V CC ) and said first node (N 1 ); a first resistor (R 1 ) linked between said first node (N 1 ) and said second power supply means (VEE); a diode stage (D 4 ) linked between said first and second nodes (N 1 , N 2 ), and having the same conduction direction as said at least three diode stages (D 1 ~D 3 ); a second resistor (R 2 ) linked between said second node (N 2 ) and said second power supply means (V EE ); a diode stage (D 0 ) linked along a backward bias direction linked between said first power supply means (V CC ) and said write power supply means ( V P ); a short-circuited junction type PROM cell (PC) linked between said write power supply means (Vp) and said second node (N 2 ); a switching element (Q 1 ), linked between said second node (N 2 ) and said second power supply means (VEE); and output means (Q 2 ~Q 4 , R 3 ), connected to said first and second nodes (N 1 , N 2 ), for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 21

An information memory device comprising: a first power supply means (V CC ); a second power supply means (V EE ); a write power supply means (Vp); first and second nodes (N 1 , N2); at least three diode stages (D 1 ~D3) along a forward bias direction between said first power supply means (V CC ) and said first node (N 1 ); a first resistor (R 1 ) linked between said first node (N 1 ) and said second power supply means (VEE); a diode stage (D 4 ) linked between said first and second nodes (N 1 , N 2 ), and having the same conduction direction as said at least three diode stages (D 1 ~D 3 ); a second resistor (R 2 ) linked between said second node (N 2 ) and said second power supply means (V EE ); a diode stage (D 0 ) linked along a backward bias direction linked between said first power supply means (V CC ) and said write power supply means ( V P ); a short-circuited junction type PROM cell (PC) linked between said write power supply means (Vp) and said second node (N 2 ); a switching element (Q 1 ), linked between said second node (N 2 ) and said second power supply means (VEE); and output means (Q 2 ~Q 4 , R 3 ), connected to said first and second nodes (N 1 , N 2 ), for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 22

An information memory device comprising: a first power supply means (V CC ); a second power supply means (VEE); a write power supply means (Vp); first and second nodes (N 1 , N 2 ); at least three diode stages (D 1 ~D 3 ) along a forward bias direction between said first power supply means (V CC ) and said first node (N 1 ); a first resistor (R,) linked between said first node (N 1 ) and said second power supply means (V EE ); at least four diode stages (D 1 '~D 3 ', D 4 ) linked along a forward bias direction between said first power supply means (V CC ) and said second node (N 2 ); a second resistor (R 2 ) linked between said second node (N 2 ) and said second power supply means (VEE); a diode stage (D 0 ) linked along a backward bias direction linked between said first power supply means (V CC ) and said write power supply means (V P ); a short-circuited junction type PROM cell (PC) linked between said write power supply means (Vp) and said second node (N 2 ); a switching element (Q 1 ), linked between said second node (N 2 ) and said second power supply means (VEE); and output means (Q 2 ~Q 4 , R 3 ), connected to said first and second nodes (N 1 , N 2 ), for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 23

An information memory device comprising: a first power supply means (V CC ); a second power supply means (VEE); a write power supply means (Vp); first and second nodes (N 1 , N 2 ); at least three diode stages (D 1 ~D 3 ) along a forward bias direction between said first power supply means (V CC ) and said first node (N 1 ); a first resistor (R,) linked between said first node (N 1 ) and said second power supply means (V EE ); at least four diode stages (D 1 '~D 3 ', D 4 ) linked along a forward bias direction between said first power supply means (V CC ) and said second node (N 2 ); a second resistor (R 2 ) linked between said second node (N 2 ) and said second power supply means (VEE); a diode stage (D 0 ) linked along a backward bias direction linked between said first power supply means (V CC ) and said write power supply means (V P ); a short-circuited junction type PROM cell (PC) linked between said write power supply means (Vp) and said second node (N 2 ); a switching element (Q 1 ), linked between said second node (N 2 ) and said second power supply means (VEE); and output means (Q 2 ~Q 4 , R 3 ), connected to said first and second nodes (N 1 , N 2 ), for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 24

An information memory device comprising: a first power supply means (V CC ); a second power supply means (VEE); a write power supply means (Vp); first and second nodes ( N l , N 2 ); at least two diode stages (D 1 , D 2 ) along a forward bias direction between said first power supply means (V CC ) and said first node (N 1 ); a first resistor (R 1 ) linked between said first node (N 1 ) and said second power supply means (VEE) a diode stage (D 4 ) linked between said first and second nodes (N 1 , N2), and having the same conduction direction as said at least two diode stages (D 1 , D 2 ); a second resistor (R 2 ) linked between said second node (N 2 ) and said second power supply means (VEE); a resistor (R 0 ) linked between said first power supply means (V CC ) and said write power supply means (V P ); a short-circuited junction type PROM cell (PC) linked between said write power supply means (Vp) and said second node (N 2 ); a switching element (Q 1 ), linked between said second node (N 2 ) and said second power supply means (VEE); and output means (Q 2 ~Q 4 , R 3 ), connected to said first and second nodes (N 1 , N2), for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 25

An information memory device comprising: a first power supply means (V CC ); a second power supply means (VEE); a write power supply means (Vp); first and second nodes ( N l , N 2 ); at least two diode stages (D 1 , D 2 ) along a forward bias direction between said first power supply means (V CC ) and said first node (N 1 ); a first resistor (R 1 ) linked between said first node (N 1 ) and said second power supply means (VEE) a diode stage (D 4 ) linked between said first and second nodes (N 1 , N2), and having the same conduction direction as said at least two diode stages (D 1 , D 2 ); a second resistor (R 2 ) linked between said second node (N 2 ) and said second power supply means (VEE); a resistor (R 0 ) linked between said first power supply means (V CC ) and said write power supply means (V P ); a short-circuited junction type PROM cell (PC) linked between said write power supply means (Vp) and said second node (N 2 ); a switching element (Q 1 ), linked between said second node (N 2 ) and said second power supply means (VEE); and output means (Q 2 ~Q 4 , R 3 ), connected to said first and second nodes (N 1 , N2), for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 26

An information memory device comprising: a first power supply means (V CC ); a second power supply means (VEE); a write power supply means (V P ); first, second, and third nodes (N 0 , N 1 , N 2 ); a diode stage (D 0 ) linked along a forward bias direction between said first power supply means (V CC ) and said first node (N 0 ); at least two diode stages (D 1 , D 2 ) along a forward bias direction between said first and second nodes (N 0 , N l ); a first resistor (R 1 ) linked between said second node (N l ) and said second power supply means (V EE ); a diode stage (D 4 ) linked between said first and second nodes (N 1 , N 2 ), and having the same conduction direction as said at least two diode stages (D 1 , D2); a second resistor (R 2 ) linked between said second node (N 2 ) and said second power supply means (V EE ); a short-circuited junction type PROM cell (PC) linked between said write power supply means ( V p) and said third node (N 2 ); a switching element (Q 1 ), linked between said third node (N 2 ) and said second power supply means (VEE); and output means (Q 2 ~Q 4 , R 3 ), connected to said second and third nodes (N 1 , N 2 ), for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 27

An information memory device comprising: a first power supply means (V CC ); a second power supply means (VEE); a write power supply means (V P ); first, second, and third nodes (N 0 , N 1 , N 2 ); a diode stage (D 0 ) linked along a forward bias direction between said first power supply means (V CC ) and said first node (N 0 ); at least two diode stages (D 1 , D 2 ) along a forward bias direction between said first and second nodes (N 0 , N l ); a first resistor (R 1 ) linked between said second node (N l ) and said second power supply means (V EE ); a diode stage (D 4 ) linked between said first and second nodes (N 1 , N 2 ), and having the same conduction direction as said at least two diode stages (D 1 , D2); a second resistor (R 2 ) linked between said second node (N 2 ) and said second power supply means (V EE ); a short-circuited junction type PROM cell (PC) linked between said write power supply means ( V p) and said third node (N 2 ); a switching element (Q 1 ), linked between said third node (N 2 ) and said second power supply means (VEE); and output means (Q 2 ~Q 4 , R 3 ), connected to said second and third nodes (N 1 , N 2 ), for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 28

An information memory device comprising: a first power supply means (VCC); a second power supply means (V EE ); a write power supply means (Vp); first and second nodes (N 1 , N2); at least two diode stages (D 1 , D 2 ) along a forward bias direction between said first power supply means (V CC ) and said first node (N 1 ); a first resistor (R 1 ) linked between said first node (N 1 ) and said second power supply means (VEE); at least three diode stages (D 1 ', D 2 ', D 4 ) linked along a forward bias direction between said first power supply means (V CC ) and said second node (N 2 ); a second resistor (R 2 ) linked between said second node (N 2 ) and said second power supply means (V EE ); a diode stage (D 0 ) linked along a backward bias direction linked between said first power supply means (V CC ) and said write power supply means (Vp); and a short-circuited junction type PROM cell (PC) linked between said write power supply means ( V p) and said second node (N 2 ); a switching element (Q 1 ), linked between said second node (N 2 ) and said second power supply means (VEE); and output means (Q 2 ~Q 4 , R 3 ), connected to said first and second nodes (N 1 ,-N 2 ), for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).

Claim 29

An information memory device comprising: a first power supply means (VCC); a second power supply means (V EE ); a write power supply means (Vp); first and second nodes (N 1 , N2); at least two diode stages (D 1 , D 2 ) along a forward bias direction between said first power supply means (V CC ) and said first node (N 1 ); a first resistor (R 1 ) linked between said first node (N 1 ) and said second power supply means (VEE); at least three diode stages (D 1 ', D 2 ', D 4 ) linked along a forward bias direction between said first power supply means (V CC ) and said second node (N 2 ); a second resistor (R 2 ) linked between said second node (N 2 ) and said second power supply means (V EE ); a diode stage (D 0 ) linked along a backward bias direction linked between said first power supply means (V CC ) and said write power supply means (Vp); and a short-circuited junction type PROM cell (PC) linked between said write power supply means ( V p) and said second node (N 2 ); a switching element (Q 1 ), linked between said second node (N 2 ) and said second power supply means (VEE); and output means (Q 2 ~Q 4 , R 3 ), connected to said first and second nodes (N 1 ,-N 2 ), for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell (PC).