Patent EP0178447A2 successfully refreshed from Google Patents.
EP0178447A2
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A manufacturing method of an integrated circuit based on semiconductor-on-insulator technology
Assignee: Fujitsu Ltd
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Filing: 1985-09-06
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Granted: —
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Expires: 2005-09-06
Abstract
Abstract Random layout of devices or active regions of the devices is allowed for a semiconductor integrated circuit based on an SOI technology using an anti-reflecting film (14). Openings (123) are provided for the anti-reflecting film (14) 'formed on a polycrystalline silicon layer (13), corresponding to the device regions wherein devices or active regions of the devices are to be formed. An orverlapped scan of a laser (LB) beam having diameter larger than the dimension of the openings (123) is applied on the silicon layer (13) through the openings and circumferential anti-reflecting film (14). Concaved temperature profile is achieved along every directions (m) across the openings due to the enhanced beam (LB) absorption by the circumferential anti-reflecting film (14), hence recrystallization nucleation of the silicon layer initiates at the center of each opening during the laser beam scan. Thus, self-aligned single crystal regions (113) are fabricated in the polycrystalline silicon layer (13) at the respective predetermined device regions. The channel region of an IG-FET is exclusively formed in the single crystal region (113) and the source or drain regions are formed in adjacent polysilicon regions.
Inventors
- 👤 Ryoichi Mukai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 12:35
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D30/00; H10D30/60; H10D30/67; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744; H10D84/0123; H10D84/0126; H10D88/00; H10D88/01; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/38; H10P14/3802; H10P32/00; H10P32/30; H10P32/302; H10P34/00; H10P34/40; H10P34/42; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10W10/011; H10W10/014; H10W10/17; Y; Y10; Y10S; Y10S148/00; Y10S148/09; Y10S148/091
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
104 words
A fabrication method of a semiconductor device, comprising the steps of: forming an amorphous or polycrystalline semiconductor layer on an amorphous insulating layer; forming an anti-reflecting film to a light beam on said semiconductor layer; selectively forming openings at respective predetermined portions of said anti-reflecting film; irradiating said light beam to an area of surface of said anti-reflecting film, said area including at least one of said openings, on conditions that said semiconductor layer is recrystallized to be free of grain boundaries at said opening; and forming a semiconductor device or active region of said device in said recrystallized semiconductor layer at said opening,
Claim 2
Dependent Claim
104 words
A fabrication method of a semiconductor device, comprising the steps of: forming an amorphous or polycrystalline semiconductor layer on an amorphous insulating layer; forming an anti-reflecting film to a light beam on said semiconductor layer; selectively forming openings at respective predetermined portions of said anti-reflecting film; irradiating said light beam to an area of surface of said anti-reflecting film, said area including at least one of said openings, on conditions that said semiconductor layer is recrystallized to be free of grain boundaries at said opening; and forming a semiconductor device or active region of said device in said recrystallized semiconductor layer at said opening,
Claim 3
Dependent Claim
18 words
A fabrication method of a semiconductor device as set forth in claim 1, wherein said semiconductor is silicon.
Claim 4
Dependent Claim
56 words
A fabrication method of a semiconductor device as set forth in claim 1, further comprising a step of forming an insulated gate electrode on said recrystallized region of said semiconductor layer, said insulated gate electrode comprising a gate electrode and an insulating layer formed between said gate electrode and said recrystallized region of said semiconductor layer.
Claim 5
Dependent Claim
50 words
A fabrication method of a semiconductor device as set forth in claim 3, further comprising a step of forming respective regions for source and drain in said semiconductor layer, said source and drain regions facing each other across said recrystallized region of said semiconductor layer and abutting said recrystallized region.
Claim 6
Dependent Claim
18 words
A fabrication method of a semiconductor device as set forth in claim 3, wherein said semiconductor is silicon.
Claim 7
Dependent Claim
22 words
A fabrication method of a semiconductor device as set forth in claim 5, wherein said insulating layer is a silicon dioxide layer.
Claim 8
Dependent Claim
28 words
A fabrication method of a semiconductor device as set forth in claim 6, wherein said silicon dioxide layer is formed by using LPCVD (low pressure chemical vapor deposition).
Claim 9
Dependent Claim
34 words
A fabrication method of a semiconductor device as set forth in claim 6, wherein said insulating silicon dioxide layer is formed by thermally oxidizing the surface of said recrystallized region of said semiconductor layer.
Claim 10
Dependent Claim
22 words
A fabrication method of a semiconductor device as set forth in claim 1, wherein said anti-reflecting layer comprises a silicon nitride layer.
Claim 11
Dependent Claim
23 words
A fabrication method of a semiconductor device as set forth in claim 9, wherein said anti-reflecting layer further comprises underlying silicon dioxide layer.
Claim 12
Dependent Claim
21 words
A fabrication method of a semiconductor device as set forth in claim 1, wherein said light beam is a laser beam.
Claim 13
Dependent Claim
23 words
A fabrication method of a semiconductor device as set forth in claim 11, wherein said laser beam is an Ar ion laser beam.
Claim 14
Dependent Claim
33 words
A fabrication method of a semiconductor device as set forth in claim 1, wherein said light beam is scanned over said anti-reflecting layer so that semiconductor regions at said openings are consecutively recrystallized.
Claim 15
Dependent Claim
41 words
An insulated-gate fiel.d-effect transistor (IG-FET) fabricated in a semiconductor layer formed on an amorphous insulating layer (24, 4, 12, 40), said semiconductor layer (22, 6, 13, 41) having a recrystallized region in which channel region of said IG-FET is exclusively formed.
Claim 16
Dependent Claim
41 words
An insulated-gate fiel.d-effect transistor (IG-FET) fabricated in a semiconductor layer formed on an amorphous insulating layer (24, 4, 12, 40), said semiconductor layer (22, 6, 13, 41) having a recrystallized region in which channel region of said IG-FET is exclusively formed.
References Cited (Backward Citations)
No citation records indexed.
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