Non-volatile dynamic random access memory cell

Claim 2

Non-volatile dynamic memory cell comprising a semiconductor substrate of a first conductivity type having a first region functioning as a dynamic storage node for storing first and second logic states, a second region of a second conductivity type, and a third region disposed between said first and second regions, a transfer device for selectively coupling data signals between said second region and said first region, said transfer device having a control electrode, characterized by a floating gate electrode (14A) disposed above and insulated from said third region (12C), first and second charge injection means (24A, 24B) disposed on said floating gate electrode ( 14 A) for injecting charge into and removing charge from, respectively, said floating gate electrodes (16A, 16B) disposed on said first and second charge injection means (24A, 248), respectively, said first and second control electrodes (16A, 1 6B) receiving first and second control signals (V WL' V CG ), respectively, said first and second control electrodes (16A, 16B) initiating said charge transfer by said first and second charge injection means (24A, 248), respectively, as a function of the voltage on said first region (12C), said logic states being overwritten into said floating gate electrode (14A), one of said control electrodes (16A) being electrically in common with said control electrode of said transfer device.

Claim 3

Memory cell in accordance with claim 1, characterized in that said second region (18) is designed as a diffused bit line receiving a control voltage (V BL ), and that said transfer device comprises a word line device the gate electrode whereof is in common with the control electrode ( 1 6A) of said transfer device, and the drain electrode whereof is in common with said diffused bit line (18).

Claim 4

Memory cell in accordance with claim 1, characterized in that said floating gate electrode (1 4 A) is comprises of a first layer of polycrystalline silicon, and that said first and second control electrodes (16A, 16B) are comprises of a second layer of polycrystalline silicon.

Claim 5

Memory cell in accordance with claim 1, characterized in that each of said first and second charge injection means (24A, 24B) is comprises of a layer of dual electron injector structure material and has an electrical characteristic analogous to that of two back-to-back connected diodes.

Claim 6

Memory cell in accordance with claim 1, characterized in that it comprises a storage plate electrode (14B) disposed on and insulated from said semiconductor substrate (10), said storage plate electrode (14B) at least partially overlaying said first region of said substrate (10).

Claim 7

Memory cell for storing data in volatile and non- volatile forms, the non-volatile storage having an overwrite capability, comprising a semiconductor substrate of a first conductivity type having a first surface region which comprises a dynamic storage node, a second surface region of a second conductivity type, and a third region disposed between said first and second regions, characterized in that said second region is designed as a diffused bit line (18), that a charge transfer device having a gate electrode (16A) is disposed above and insulated from said semiconductor substrate (10) for selectively coupling data signals between said bit line ( 1 8) and said first region to control the voltage of said first region, that a non-volatile storage means ( 1 4A) is disposed above said third region and being insulated therefrom, and that first and second control gates (24B + 16B; 24A + 16A) are disposed on said non-volatile storage means (14A) and receive first (V WL ) and second (V CG ) control signals, respectively, said first control gate (24B + 16B) removing charge from said first region of said substrate (10) is storing a first volatile indicative of a first logic state, and said second control gate (24A + 1 6A) injecting charge into said non-volatile storage means (14A) when said first region of said substrate (10) is storing a second voltage indicative of a second logic state, said logic states being overwritten from said dynamic storage node into said non-volatile storage means (14A).

Claim 8

Memory cell for storing data in volatile and non- volatile forms, the non-volatile storage having an overwrite capability, comprising a semiconductor substrate of a first conductivity type having a first surface region which comprises a dynamic storage node, a second surface region of a second conductivity type, and a third region disposed between said first and second regions, characterized in that said second region is designed as a diffused bit line (18), that a charge transfer device having a gate electrode (16A) is disposed above and insulated from said semiconductor substrate (10) for selectively coupling data signals between said bit line ( 1 8) and said first region to control the voltage of said first region, that a non-volatile storage means ( 1 4A) is disposed above said third region and being insulated therefrom, and that first and second control gates (24B + 16B; 24A + 16A) are disposed on said non-volatile storage means (14A) and receive first (V WL ) and second (V CG ) control signals, respectively, said first control gate (24B + 16B) removing charge from said first region of said substrate (10) is storing a first volatile indicative of a first logic state, and said second control gate (24A + 1 6A) injecting charge into said non-volatile storage means (14A) when said first region of said substrate (10) is storing a second voltage indicative of a second logic state, said logic states being overwritten from said dynamic storage node into said non-volatile storage means (14A).