Logical gate circuit

Claim 2

A logical gate circuit comprising a switching transistor (Q 1 ), an active load circuit (C) connected to a collector of said switching transistor, said switching transistor being cut OFF when an input signal (IN) is at a first level (L level) and being made ON when said input signal is at a second level (H level), a control transistor means (B) connected to a base portion of said switching transistor and made ON or OFF in response to a second level and a first level of an output voltage (OUT) of said switching transistor, and an input transistor means connected (A) / in series with said control transistor means and made ON and OFF when said input signal is at the second level (H) and at the first level (L), respectively.

Claim 3

A logical gate circuit according to claim 1, further comprising: a first power source (V H ) and a second power source (V L ); and wherein: said switching transistor (Q,) is an NPN type bipolar transistor, an emitter of said switching transistor being connected to said second power source, and a collector of said switching transistor being connected to an output terminal; said active load circuit (C) is a P channel MIS transistor (Q 2 ), a source of said MIS transistor being connected to said first power source, a drain of said MIS transistor being connected to said output terminal, and a gate of said MIS transistor being connected to an input terminal, said control transistor means (B) is a M IS transistor (Q 4 ), a source of which is connected to the base of said switching transistor, and a gate of which is connected to the output terminal; and said input transistor means (A) is a MIS transistor (Q 3 ) having control (Q ) a source connected to the drain of said/MIS transistor/, a gate connected to said input terminal, and a drain connected to said first power source.

Claim 4

A logical gate circuit according to claim 2, load (C) said active/circuit /further comprising an NPN transistor (Q 9 ) between said P channel MIS transistor (Q 10 , equivalent to Q 2 ) and the output terminal.

Claim 5

A logical gate circuit according to claim 2 or claim 3, wherein the output terminal is connected to an input terminal of a next stage gate, and said input terminal of said next stage gate is a high impedance input.

Claim 6

A logical gate circuit according to claim 1, further comprising a first power source (V H ) and a second power source (V L ) , and equivalent to Q wherein said switching transistor (Q 5 is a PNP type bipolar transistor, an emitter of said switching transistor being connected to said first power source, and; a collector of said switching transistor being connected to an output terminal; said active load circuit/is an N channel MIS transistor (Q6), a source of said MIS transistor being connected to said second power source, a drain of said MIS transistor being connected to said output terminal and a gate of said MIS transistor being con- nec t ed to an input terminal, means ( B ) said control transistor/is a P channel MIS transistor (Q 8 ), a source of said P channel MIS transistor being connected to the base of said (Q 5 ) switching transistor/and/agate of said P channel MIS transistor being connected to the output terminal, and means (A) said input transistor/is a P channel MIS transistor (Q 7 ) providing a source connected to the drain of said P channel MIS (Q 8 ) of said control transistor means, transistor / a gate connected to said input terminal,and a drain connected to said second power source.

Claim 7

A logical gate circuit according to claim 5, said active load circuit further comprising a PNP transistor (Q 11 ) connected between said N channel MIS transistor (Q 12 , equivalent to Q 6 and the output terminal.

Claim 8

A logical gate circuit according to claim 5 or claim 6, wherein the output terminal is connected to an input terminal of a next stage gate, and said input terminal of said next stage gate is a high impedance input.

Claim 9

A logical gate circuit comprising a PNP transistor (Q 5 ) and an NPN transistor (Q 1 ) each having a collector connected to a common output terminal and each having an emitter connected to a first power source (V H ) and a second power source (V L ) respectively, a first and a second N channel MIS transistor means (Q 4 , Q3) connected in series between the base of said NPN transistor (Q 1 ) and said first power source (V H ), a first /P-channel MIS. and a second transistor means (Q 8 , Q 7 ) connected in series between the base of said PNP transistor (Q 5 ) an said second power source (V L ), and said first N channel MIS transistor means Q 4 ) and said first P channel MIS transistor means (Q 8 ) are made ON and OFF by an output signal, and said second N channel MIS transistor means (Q 3 ) and said second P channel MIS transistor means (Q 7 ) are made ON and OFF by an input signal.

Claim 10

A logical gate circuit comprising a PNP transistor (Q 5 ) and an NPN transistor (Q 1 ) each having a collector connected to a common output terminal and each having an emitter connected to a first power source (V H ) and a second power source (V L ) respectively, a first and a second N channel MIS transistor means (Q 4 , Q3) connected in series between the base of said NPN transistor (Q 1 ) and said first power source (V H ), a first /P-channel MIS. and a second transistor means (Q 8 , Q 7 ) connected in series between the base of said PNP transistor (Q 5 ) an said second power source (V L ), and said first N channel MIS transistor means Q 4 ) and said first P channel MIS transistor means (Q 8 ) are made ON and OFF by an output signal, and said second N channel MIS transistor means (Q 3 ) and said second P channel MIS transistor means (Q 7 ) are made ON and OFF by an input signal.

Claim 11

A logical gate circuit according to claim 1, load (C) wherein said active / circuit /is formed by a plurality of enhancement type transistors (Q2a, /Q2b ... Q2n) connected in parallel, and said input transistor means is formed by a plurality of enhancement type transistors (Q3a,/Q3b, ... , Q 3n) connected in series, and each one of n one of input terminals is connected to a respective/ the gates of said transistors ( Q 2a , Q 2b ... , Q 2 n) of said active lead circuit and also to a respective one of the gates of said transistors ( Q 3a, Q 3b... Q 3n of said input transistor means.

Claim 12

A logical gate circuit according to claim 1, wherein said active load circuit(C) is) formed by a plurality of enhancement type transistors (Q 2A' Q 2B , ..., Q 2N ) connected in series, and said input transistor means (A) is formed by a plurality of enhancement type transistor (Q 3A , Q 3B' ..., Q 3N ) connected in parallel, and each one of n input terminals is connected to a respective one of the gates of the transistors (2A, 2B, ..., Q 2N ) of said active load circuit and also to a respective one of the gates of said transistors Q 3A , 3B, ..., 3N) of said input transistor means.