Dynamically controllable output logic circuit

Claim 2

An output logic circuit for controlling configuration of an an input/output port, comprising: means for providing a logic signal; register means, responsive to a clock signal, for latching said logic signal to provide a registered signal; output select means, responsive to an output select signal, for selecting said logic signal or said registered signal; feedback means for providing a feedback signal, including a feedback select means, responsive to a feedback select signal, for selecting said logic signal or said registered signal as the feedback signal; clock signal enable means, responsive to a clock enable signal, for providing said clock signal to clock said register means; clock means for providing said clock signal; means for dynamically providing said clock enable signal; means for dynamically providing said feedback select signal; and means for dynamically providing said output select signal.

Claim 3

The device of Claim 1, wherein said register means includes: means, responsive to a reset signal, for asynchronous reset of said register means; and means for dynamically providing said reset signal.

Claim 4

The device of Claim 1, wherein said register means includes: means, responsive to a preset signal, for synchronous preset of said register means; and means for dynamically providing said preset signal.

Claim 5

The circuit of Claim 1, further including: output means, responsive to an output enable signal, for providing the selected signal from said output select means as the output signal to the output port; means for dynamically providing the output enable signal.

Claim 6

The circuit of Claim 1, wherein said clock enable means includes: means for programmably selecting the polarity of the clock signal.

Claim 7

The circuit of Claim 1, further including: means, responsive to polarity select signal, for selecting the polarity of the clock signal; and means for dynamically providing said polarity select signal.

Claim 8

The circuit of Claim 1, wherein: said register means provides said registered signal and a complement of said registered signal; and further including means complementing said logic signal to provide a complement of said logic signal; and said output select means selects said registered signal, said complement of said registered signal, said logic signal, or said complement of said logic signal as said output signal.

Claim 9

The circuit of Claim 1, further comprising: means in .communication with the input/output port for providing data signals from the input/output port as feedback.

Claim 10

In a programmable array logic device having a plurality of logic cells for dynamically generating logic signals, and a second plurality of combinatorial means for combining a subset of said logic signals to generate a plurality of combinatorial signals, a circuit for controlling configuration of an input/output port, comprising: register means, responsive to a clock signal, for latching one of said combinatorial signals; clock enable means, responsive to a clock enable signal, for providing the clock signal to clock said register means; and means for dynamically providing said clock enable signal.

Claim 11

In a programmable array logic device having a plurality of logic cells for dynamically generating logic signals, and a second plurality of combinatorial means for combining a subset of said logic signals to generate a plurality of combinatorial signals, a circuit for controlling configuration of an input/output port, comprising: register means, responsive to a clock signal, for latching one of said combinatorial signals; clock enable means, responsive to a clock enable signal, for providing the clock signal to clock said register means; and means for dynamically providing said clock enable signal.

Claim 12

The circuit of Claim 9, wherein said clock enable means includes: means for programmably selecting the polarity of said clock signal.

Claim 13

1 1. The circuit of Claim 9, further including: means, responsive to polarity select signal, for selecting the polarity of the clock signal; and means for dynamically providing said polarity select signal.

Claim 14

In a programmable array logic device having a plurality of logic cells for dynamically generating logic signals, and a second plurality of combinatorial means for combining a subset of said logic signals to generate a plurality of combinatorial signals, a circuit for controlling configuration of an input/output port, comprising: register means, for latching one of said combinatorial signals and providing a registered signal; output select means, responsive to an output select signal, for selecting said registered signal or said one combinatorial signal as the output signal; and means for dynamically providing said output select signal.

Claim 15

In a programmable array logic device having a plurality of logic cells for dynamically generating logic signals, and a second plurality of combinatorial means for combining a subset of said logic signals to generate a plurality of combinatorial signals, a circuit for controlling configuration of an input/output port, comprising: register means, for latching one of said combinatorial signals and providing a registered signal; output select means, responsive to an output select signal, for selecting said registered signal or said one combinatorial signal as the output signal; and means for dynamically providing said output select signal.

Claim 16

The circuit of Claim 12, wherein: said register means provides said registered signal and a complement of said registered signal; and further including means complementing said one combinatorial signal to provide a complement of said combinatorial signal; and said output select means selects said registered signal, said complement of said registered signal, said one combinatorial signal, or said complement of said one combinatorial signal as said output signal.

Claim 17

The circuit of Claim 10, further comprising: output enable means, responsive to an output enable signal, for enabling the output signal at an input/output port; and means for dynamically providing said output enable signal.

Claim 18

The circuit of Claim 14, further comprising: means in communication with said input/output port for providing data signals from said input/output port as feedback to said programmable logic cell array means.

Claim 19

In a programmable array logic device having a plurality of logic cells for dynamically .generating logic signals, and a second plurality of combinatorial means for combining a subset of said logic signals to generate a plurality of combinatorial signals, a circuit for controlling configuration of an input/output port, comprising: register means for latching one of said combinatorial signals to provide a registered signal; feedback means for providing feedback data to the programmable logic cell array including feedback select means, responsive to a feedback select signal, for selecting said registered signal or said one combinatorial signal as said feedback data; and means for dynamically providing said feedback select signal.

Claim 20

In a programmable array logic device having a plurality of logic cells for dynamically .generating logic signals, and a second plurality of combinatorial means for combining a subset of said logic signals to generate a plurality of combinatorial signals, a circuit for controlling configuration of an input/output port, comprising: register means for latching one of said combinatorial signals to provide a registered signal; feedback means for providing feedback data to the programmable logic cell array including feedback select means, responsive to a feedback select signal, for selecting said registered signal or said one combinatorial signal as said feedback data; and means for dynamically providing said feedback select signal.

Claim 21

A programmable array logic device having a plurality of input/output ports, comprising: a programmable logic cell array means responsive to a plurality of data signals for providing a set of logic signals; combinatorial means for combining a subset of said set of logic signals to provide a combinatorial signal; output logic means for controlling configuration of output including register means, responsive to a clock signal, for latching said combinatorial signal to provide a registered signal, output select means, responsive to an output select signal, for selecting said combinatorial signal or said registered signal, feedback means for providing a feedback signal as data to said programmable logic cell array means including a feedback select means, responsive to a feedback select signal, for selecting said combinatorial signal or said registered signal as said feedback signal, and clock signal enable means, responsive to a clock enable signal, for providing said clock signal to clock said register means; output means, responsive to an output enable signal, for providing the selected signal from said output select means as an output signal at one of the input/output ports, clock means for providing the clock signal; means for providing at least one logic signal or a combination of logic signals from said set of logic signals as the clock enable signal; means for providing at least one logic signal or a combination of logic signals from said set of logic signals as the feedback select signal; means for providing at least one logic signal or a combination of logic signals from said set of logic signals as the output select signal; means for providing at least one logic signal or a combination of logic signals from said set of logic signals as the output enable signal.

Claim 22

A programmable array logic device having a plurality of input/output ports, comprising: a programmable logic cell array means responsive to a plurality of data signals for providing a set of logic signals; combinatorial means for combining a subset of said set of logic signals to provide a combinatorial signal; output logic means for controlling configuration of output including register means, responsive to a clock signal, for latching said combinatorial signal to provide a registered signal, output select means, responsive to an output select signal, for selecting said combinatorial signal or said registered signal, feedback means for providing a feedback signal as data to said programmable logic cell array means including a feedback select means, responsive to a feedback select signal, for selecting said combinatorial signal or said registered signal as said feedback signal, and clock signal enable means, responsive to a clock enable signal, for providing said clock signal to clock said register means; output means, responsive to an output enable signal, for providing the selected signal from said output select means as an output signal at one of the input/output ports, clock means for providing the clock signal; means for providing at least one logic signal or a combination of logic signals from said set of logic signals as the clock enable signal; means for providing at least one logic signal or a combination of logic signals from said set of logic signals as the feedback select signal; means for providing at least one logic signal or a combination of logic signals from said set of logic signals as the output select signal; means for providing at least one logic signal or a combination of logic signals from said set of logic signals as the output enable signal.

Claim 23

The device of Claim 17, wherein said register means of said output logic means includes: means, responsive to a reset signal, for asynchronous reset of said register means, and means for providing at least one logic signal or a combination of logic signals from said set of logic signals as said reset signal.

Claim 24

The device of Claim 17, wherein said register means of said output logic means includes: means, responsive to a preset signal, for synchronous preset of said register means, and means for providing at least one logic signal or a combination of logic signals from said set of logic signals as said preset signal.

Claim 25

The circuit of Claim 17, wherein said clock enable means includes: means for programmably controlling the polarity of said clock signal.

Claim 26

The circuit of Claim 17, further including: means, responsive to polarity select signal, for selecting the polarity of the clock signal; and means for dynamically providing said polarity select signal.

Claim 27

The circuit of Claim 17, wherein: said register means provides said registered signal and a complement of said registered signal; and further including means complementing said combinatorial signal to provide a complement of said combinatorial signal; and said output select means selects said registered signal, said complement of said registered signal, said combinatorial signal, or said complement of said combinatorial signal as said output signal.

Claim 28

The circuit of Claim 17, further comprising: means in communication with said input/output port for providing data signals from said input/output port as feedback to said programmable logic cell array means.