Programmable data path width in a programmable unit having plural levels of subinstructions sets

Claim 2

A processing system comprising: an arithmetic logic unit; a control store to supply control instructions to said arithmetic logic unit; said arithmetic logic unit including data buses all of which are n bits wide, said arithmetic logic unit also including means to select whether all the bits for said data buses are to be used or only m bits of said data buses are to be used where m is less than n; said arithmetic logic unit being coupled to said control store to receive a control instruction specifying whether m or n bits of said data buses are to be used.

Claim 3

A system according to Claim 1 wherein: said arithmetic logic unit includes an adder unit coupled to said control store to receive information as to whether a carry signal is to be generated when the output of said adder unit is to be m bits wide or n bits wide.

Claim 4

A system according to Claim 2 wherein: said arithmetic logic unit includes shifting means coupled to said control store to receive control information specifying whether said shifting means is to shift data end around by up to n bits or up to m + n.

Claim 5

A processing system including an arithmetic logic unit having various functional units, said system comprisings a first level subinstruction storage means; a second level subinstruction storage means; and a control register; said first level subinstruction storage means containing first level subinstructions which include an address to said second level subinstruction storage means, said first level storage means also including second level subinstructions which contain control signals; said second level subinstruction storage means containing other second level subinstructions having control signals contained therein; said control register to be coupled to said first level subinstruction storage means and said second level subinstruction storage means to receive second level subinstructions control signals from one or the other of said storage means, said control register further being coupled to said arithmetic logic unit to supply said control signals to said various functional units of said arithmetic logic units; said arithmetic logic unit also including data buses, all of which are n bits wide, said arithmetic logic unit further including means to select n bits of said data buses for use, or m bits of said data buses for use where m is less than n, said selection means being coupled to said first level subinstruction means to receive information as to whether m or n bits of said data buses are to be used.

Claim 6

A processing system including an arithmetic logic unit having various functional units, said system comprisings a first level subinstruction storage means; a second level subinstruction storage means; and a control register; said first level subinstruction storage means containing first level subinstructions which include an address to said second level subinstruction storage means, said first level storage means also including second level subinstructions which contain control signals; said second level subinstruction storage means containing other second level subinstructions having control signals contained therein; said control register to be coupled to said first level subinstruction storage means and said second level subinstruction storage means to receive second level subinstructions control signals from one or the other of said storage means, said control register further being coupled to said arithmetic logic unit to supply said control signals to said various functional units of said arithmetic logic units; said arithmetic logic unit also including data buses, all of which are n bits wide, said arithmetic logic unit further including means to select n bits of said data buses for use, or m bits of said data buses for use where m is less than n, said selection means being coupled to said first level subinstruction means to receive information as to whether m or n bits of said data buses are to be used.

Claim 7

A system according to Claim 4 wherein: said arithmetic logic unit includes an adder unit coupled to said first level storage means to receive information as to whether a carry signal is to be generated when the output of said adder is to be m bits wide or n bits wide.

Claim 8

A processing system according to Claim 5 wherein: said arithmetic logic unit includes shifting means coupled to said first level control store to receive information specifying whether such shifting means is to shift data end around by up to n bits or m + n bits.

Claim 9

A system according to Claim 4 further including: decoder means coupled to said first level subinstruction storage means to receive the first set of bits in said first level subinstruction to determine whether said first level subinstruction includes an address to said second level memory or includes a second level subinstruction; and multiplexing means coupled to said decoder means, said multiplexing means also being coupled to said first level subinstruction storage means and said second level subinstruction storage means to select one of said storage means to supply a second level subinstruction to said control register.

Claim 10

A system according to Claim 6 further including: a control unit; and memory means to store machine language instructions, said memory means being coupled to said control unit to supply said machine language instructions thereto; said control unit including means to form first level subinstruction storage means addresses from said machine language instructions.

Claim 11

A system according to Claim 8 further including: sequencing means coupled to said control unit and to said first level subinstruction storage means to receive said first level subinstruction storage means addresses to address said first level subinstruction storage means.

Claim 12

A system according to Claim 9 including: an external bus; and external bus interface means coupled between said external bus and said control unit; said external bus being coupled to said memory means to receive said machine language instructions and data.

Claim 13

A processing system including an arithmetic logic unit having various functional units, said system comprising: a first level subinstruction storage means; a second level subinstruction storage means; and a control register; said first level subinstruction storage means containing first level subinstructions which include an address to said second level subinstructon storage means, said first level storage means also including second level subinstructions which contain control signals; said second level subinstructon storage means containing other second level subinstructions having control signals contained therein; said control register being coupled to said first level subinstruction storage means and said second level subinstruction storage means to receive second level subinstruction control signals from one or the other of said storage means, said control register further being coupled to said arithmetic logic unit to supply said control signals to said various functional units of said arithmetic logic unit.

Claim 14

A processing system including an arithmetic logic unit having various functional units, said system comprising: a first level subinstruction storage means; a second level subinstruction storage means; and a control register; said first level subinstruction storage means containing first level subinstructions which include an address to said second level subinstructon storage means, said first level storage means also including second level subinstructions which contain control signals; said second level subinstructon storage means containing other second level subinstructions having control signals contained therein; said control register being coupled to said first level subinstruction storage means and said second level subinstruction storage means to receive second level subinstruction control signals from one or the other of said storage means, said control register further being coupled to said arithmetic logic unit to supply said control signals to said various functional units of said arithmetic logic unit.

Claim 15

A system according to Claim 11 further including: decoder means coupled to said first level subinstruction storage means to receive the first set of bits in said first level subinstruction to determine whether said first level subinstruction includes an address to said second level memory or includes a second level subinstruction; and multiplexing means coupled to said decoder means, said multiplexing means also being coupled to said first level subinstruction storage means and said second level subinstruction storage means to select one of said storage means to supply a second level subinstruction to said control register.

Claim 16

A system according to Claim 12 further including: a control unit; and memory means to store machine language instructions, said memory means being coupled to said control unit to supply said machine language instructions thereto; said control unit including means to form first level subinstruction storage means addresses from said machine language instructions.

Claim 18

A system according to Claim 13 further including: sequencing means coupled to said control unit and to said first level subinstruction storage means to receive said first level subinstruction storage means addresses to address said first level subinstruction storage means.

Claim 20

17 . A system according to Claimll wherein: said arithmetic logic unit includes adder means, input registers coupled to said adder means and an output register coupled to said adder means; said control signals in said second level subinstructions being divided into fields, and said control register being coupled to the respective functional units to supply control signals thereto.

Claim 21

1 8. A processing system including a control unit and an arithmetic logic unit having various functional units, said system comprising: a first level subinstruction storage means; a second level subinstruction storage means; memory means to store machine language instructions, said memory means being coupled to said control unit to supply said machine language instructions thereto; and a control register; said first level subinstruction storage means containing first level subinstructions which include an address to said second level subinstruction storage means, said first level storage means also including second level subinstructions which contain control signals; said second level subinstruction storage means containing other second level subinstructions having control signals contained therein; said control unit including means to form first level subinstruction storage means addresses from said machine language instructions; said control register being coupled to said first level subinstruction storage means and said second level subinstruction storage means to receive second level subinstruction control signals from one or the other of said storage means, said control register further being coupled to said arithmetic logic unit to supply said control signals to said various functional units of said arithmetic logic unit.

Claim 22

1 8. A processing system including a control unit and an arithmetic logic unit having various functional units, said system comprising: a first level subinstruction storage means; a second level subinstruction storage means; memory means to store machine language instructions, said memory means being coupled to said control unit to supply said machine language instructions thereto; and a control register; said first level subinstruction storage means containing first level subinstructions which include an address to said second level subinstruction storage means, said first level storage means also including second level subinstructions which contain control signals; said second level subinstruction storage means containing other second level subinstructions having control signals contained therein; said control unit including means to form first level subinstruction storage means addresses from said machine language instructions; said control register being coupled to said first level subinstruction storage means and said second level subinstruction storage means to receive second level subinstruction control signals from one or the other of said storage means, said control register further being coupled to said arithmetic logic unit to supply said control signals to said various functional units of said arithmetic logic unit.

Claim 23

19 . A system according to Claim 18 further including: decoder means coupled to said first level subinstruction storage means to receive the first set of bits in said first level subinstruction to determine whether said first level subinstruction includes an address to said second level memory or includes a second level subinstruction; and multiplexing means coupled to said decoder means, said multiplexing means also being coupled to said first level subinstruction storage means and said second level subinstruction storage means to select one of said storage means to supply a second level subinstruction to said control register.

Claim 24

20, A system according to Claim18 further including: sequencing means coupled to said control unit and to said first level subinstruction storage means to receive said first level subinstruction storage means addresses to address said first level subinstruction storage means.

Claim 25

2 1 . A system according to Claim 20 including: an external bus; and external bus interface means coupled between said external bus and said control unit; said external bus being coupled to said memory means to receive said machine language instructions and data.

Claim 26

A system according to Claim 18 wherein: said arithmetic logic unit includes adder means, input registers coupled to said adder means and an output register coupled to said adder means; said control signals in said second level subinstructions being divided into fields, and said control register being coupled to the respective functional units to supply control signals thereto.