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Patent EP0177261B1 successfully refreshed from Google Patents.
EP0177261B1
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Configurable logic array
Assignee: Xilinx Inc
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Filing: 1985-09-25
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Granted: 1990-11-22
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Expires: 2005-09-25
Abstract
No abstract record available.
Inventors
- 👤 William S. Carter
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 21:04
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
204 words
A configurable logic array comprising: a plurality of configurable logic elements (g), CLEs, each CLE having at least one input lead and at least one output lead; a general interconnect structure (L, J) comprising a plurality of general interconnect leads and a plurality of programmable general interconnect junctions for interconnecting selected ones of the general interconnect leads; one or more access junctions (A) for each input lead for connecting a corresponding general interconnect lead to said input lead; one or more access junctions (A) for each output lead for connecting the output lead to a corresponding general interconnect lead; means for programming the general interconnect junctions and the access junctions such that there is an electrical path connecting a given output lead of a given CLE to a given output lead of a given CLE, the electrical path containing two acccess junctions and at least a portion of one of the general interconnect leads; and at least one special interconnection circuit (S1, S2) which permits a selected output lead of one of the CLEs to be connected to a selected input lead of another CLE, the special interconnection circuit not containing any portion of the leads or any junction in the general interconnect structure.
Claim 2
Dependent Claim
204 words
A configurable logic array comprising: a plurality of configurable logic elements (g), CLEs, each CLE having at least one input lead and at least one output lead; a general interconnect structure (L, J) comprising a plurality of general interconnect leads and a plurality of programmable general interconnect junctions for interconnecting selected ones of the general interconnect leads; one or more access junctions (A) for each input lead for connecting a corresponding general interconnect lead to said input lead; one or more access junctions (A) for each output lead for connecting the output lead to a corresponding general interconnect lead; means for programming the general interconnect junctions and the access junctions such that there is an electrical path connecting a given output lead of a given CLE to a given output lead of a given CLE, the electrical path containing two acccess junctions and at least a portion of one of the general interconnect leads; and at least one special interconnection circuit (S1, S2) which permits a selected output lead of one of the CLEs to be connected to a selected input lead of another CLE, the special interconnection circuit not containing any portion of the leads or any junction in the general interconnect structure.
Claim 3
Dependent Claim
115 words
A configurable logic array as claimed in claim 1 comprising: a first, a second, a third and a fourth CLE, the second CLE having a first output lead and a second output lead; a first special interconnection circuit which permits an output signal on the first output lead of the second CLE to be connected to a selected input lead of the first CLE and which also permits the first output signal to be connected to a selected input lead of the third; and a second special interconnection circuit which permits an output signal on the second output lead of the second CLE to be connected to a selected input lead of the fourth CLE.
Claim 4
Dependent Claim
52 words
A configurable logic array as claimed in claim 1 or 2 wherein the special interconnection circuit comprises a lead connected to the selected output lead and a pass transistor for each input lead of the selected CLE connected between the lead connected to the selected output lead and the corresponding input lead.
References Cited (Backward Citations)
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