Patent EP0177105A2 successfully refreshed from Google Patents.
EP0177105A2
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EP
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Method for providing a semiconductor device with planarized contacts
Assignee: Koninklijke Philips NV
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Filing: 1985-10-01
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Granted: —
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Expires: 2005-10-01
Abstract
Abstract 57 Planarized insulating layers provided with planarized contacts are formed on semiconductor devices by forming vias (34, 36, 38) through an insulating layer (30, 24) having a generally planar exposed surface, depositing a layer of a conductive layer (40) on this upper surface of the insulating layer in an amount at least sufficient to at least partially fill all of the vias, depositing a planarized layer (42) on the exposed surface of the conductive layer (40) and then etching away the planarized layer and the conductive layer by use of an etchant that removes the planarized layer (42) and the conductive layer (40) at substantially the same rate, until the generally planar upper surface of the insulating layer is exposed.
Inventors
- 👤 Thijs Willem Bril
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 19:42
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/42; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10P50/268; H10P50/28; H10P50/286; H10P50/287; H10W20/01; H10W20/031; H10W20/062
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
181 words
A method for providing a semiconductor device with an insulating layer having a generally planar surface and planar contacts, said device comprising a semiconductor body provided with laterally electrically isolated active areas, and a first overlying patterned conductive layer, characterized in that the method comprises the steps of: forming a first insulating layer, having a generally planar upper surface, on said first conductive layer; forming at least one via to said first conductive layer or to an active area by plasma etching through said first insulating layer down to said first conductive layer or to one of said active areas; forming, on the generally planar upper surface of said first insulating layer, a second conductive layer of a thickness sufficient to at least partially fill said via; forming on said second conductive layer a planarizing layer having a generally planar upper surface; and then etching said second conductive layer and said planarizing layer with etchant that attacks said second conductive layer and said planarizing layer at substantially equal rates until the planar upper surface of said first insulating layer is exposed.
Claim 2
Independent Claim
181 words
A method for providing a semiconductor device with an insulating layer having a generally planar surface and planar contacts, said device comprising a semiconductor body provided with laterally electrically isolated active areas, and a first overlying patterned conductive layer, characterized in that the method comprises the steps of: forming a first insulating layer, having a generally planar upper surface, on said first conductive layer; forming at least one via to said first conductive layer or to an active area by plasma etching through said first insulating layer down to said first conductive layer or to one of said active areas; forming, on the generally planar upper surface of said first insulating layer, a second conductive layer of a thickness sufficient to at least partially fill said via; forming on said second conductive layer a planarizing layer having a generally planar upper surface; and then etching said second conductive layer and said planarizing layer with etchant that attacks said second conductive layer and said planarizing layer at substantially equal rates until the planar upper surface of said first insulating layer is exposed.
Claim 3
Independent Claim
381 words
A method for providing a semiconductor device with an insulating layer having a generally planar surface and planar contacts according to the steps of: in which a semiconductor body is provided with a patterned first electrically conductive layer having at least a portion protruding upward beyond adjacent parts of said conductive layer, characterized in that the method comprises the steps of: forming a first electrically insulating layer on said first electrically conductive layer and on exposed adjacent parts of said semiconductor body in a manner such that a portion of said first insulating layer protrudes upwardly beyond adjacent parts of said first insulating layer generally at the location above the protruding portion of said first conductive layer; forming an additional layer having a generally planar upper surface on said first electrically insulating layer; exposing at least part of the protruding portion of said first electrically insulating layer by etching said additional layer with etchant that attacks the material of said additional layet at a significantly greater rate than the material of said first electrically insulating layer; etching the remainder of said additional layer and said first electrically insulating layer, as it becomes exposed, with etchant that etches the materials of said first electrically insulating layer and said additional layer at substantially equal rates thereby forming a generally planar upper surface on said first electrically insulating layer; forming at least one via to said first electrically conductive layer or to an active area of said semiconductor body by plasma etching through the remainder of said first insulating layer down to said first electrically conductive layer; forming, on the upper surface of said first insulating layer, a second conductive layer of a thickness sufficient to at least partially fill said via; forming on said second conductive layer a planarizing layer having a generally planar upper surface; exposing at least part of the second conductive layer by etching said planarizing layer with etchant that attacks material of said planarizing layer at a significantly greater rate than material of said second conductive layer; and then etching said planarizing layer and said second conductive layer, as it becomes exposed, with etchant that attacks said second conductive layer and said planarizing layer at substantially equal rates until the upper surface of said first insulating layer is exposed.
Claim 4
Independent Claim
381 words
A method for providing a semiconductor device with an insulating layer having a generally planar surface and planar contacts according to the steps of: in which a semiconductor body is provided with a patterned first electrically conductive layer having at least a portion protruding upward beyond adjacent parts of said conductive layer, characterized in that the method comprises the steps of: forming a first electrically insulating layer on said first electrically conductive layer and on exposed adjacent parts of said semiconductor body in a manner such that a portion of said first insulating layer protrudes upwardly beyond adjacent parts of said first insulating layer generally at the location above the protruding portion of said first conductive layer; forming an additional layer having a generally planar upper surface on said first electrically insulating layer; exposing at least part of the protruding portion of said first electrically insulating layer by etching said additional layer with etchant that attacks the material of said additional layet at a significantly greater rate than the material of said first electrically insulating layer; etching the remainder of said additional layer and said first electrically insulating layer, as it becomes exposed, with etchant that etches the materials of said first electrically insulating layer and said additional layer at substantially equal rates thereby forming a generally planar upper surface on said first electrically insulating layer; forming at least one via to said first electrically conductive layer or to an active area of said semiconductor body by plasma etching through the remainder of said first insulating layer down to said first electrically conductive layer; forming, on the upper surface of said first insulating layer, a second conductive layer of a thickness sufficient to at least partially fill said via; forming on said second conductive layer a planarizing layer having a generally planar upper surface; exposing at least part of the second conductive layer by etching said planarizing layer with etchant that attacks material of said planarizing layer at a significantly greater rate than material of said second conductive layer; and then etching said planarizing layer and said second conductive layer, as it becomes exposed, with etchant that attacks said second conductive layer and said planarizing layer at substantially equal rates until the upper surface of said first insulating layer is exposed.
Claim 5
Dependent Claim
17 words
The method of Claim 1, characterized in that said first insulating layer comprises a silicon-dioxide containing material.
Claim 6
Dependent Claim
18 words
!ι. The method of Claim 2, characterized in that said first insulating layer comprises a silicon-dioxide- containing material.
Claim 7
Dependent Claim
16 words
The method of Claim 3, characterized in that said planarizing layer is an organic resist layer.
Claim 8
Dependent Claim
16 words
The method of Claim 4, characterized in that said planarizing layer is an organic resist layer.
Claim 9
Dependent Claim
44 words
The method of Claim 1, characterized in that said via is formed by plasma etching with an anisotropic etch, the etch rate of which is significantly greater for said material of said first insulating layer than for the material of said first conductive layer.
Claim 10
Dependent Claim
44 words
The method of Claim 2, characterized in that said via is formed by plasma etching with an anisotropic etch, the etch rate of which is significantly greater for said material of said first insulating layer than for the material of said first conductive layer.
Claim 11
Dependent Claim
44 words
The method of Claim 3, characterized in that said via is formed by plasma etching with an anisotropic etch, the etch rate of which is significantly greater for said material of said first insulating layer than for the material of said first conductive layer.
Claim 12
Dependent Claim
44 words
The method of Claim 4, characterized in that said via is formed by plasma etching with an anisotropic etch, the etch rate of which is significantly greater for said material of said first insulating layer than for the material of said first conductive layer.
Claim 13
Dependent Claim
16 words
The method of Claim 7, characterized in that said first insulating layer is a phospho-silicate glass.
Claim 14
Dependent Claim
16 words
The method of Claim 8, characterized in that the first insulating layer is a phospho-silicate glass.
Claim 15
Dependent Claim
63 words
The method of Claim 2, characterized in that the semiconductive body comprises a monocrystalline semiconductor structure having a surface provided with a patterned electrically insulating layer, an edge portion of which protrudes upward beyond adjacent semiconductor parts and adjacent parts of said insulating region, said protruding edge portion being located generally at the location of the protruding portion of said first conductive layer.
Claim 16
Dependent Claim
21 words
The method of Claim 1, characterized in that at least one of the conductive layers if formed by chemical vapor deposition.
Claim 17
Dependent Claim
21 words
The method of Claim 2, characterized in that at least one of the conductive layers is formed by chemical vapor deposition.
Claim 18
Dependent Claim
17 words
The method of Claim 14, characterized in that th E first insulating layer comprises a semiconductor oxide.
Claim 19
Dependent Claim
16 words
The method of Claim 15, characterized in that the first insulating layer comprises a semiconductor oxide.
Claim 20
Dependent Claim
18 words
The method of Claim 14, characterized in that the second conductive layer is an electrically conducting polysilicon layer.
Claim 21
Dependent Claim
18 words
The method of Claim 18, characterized in that the second conductive layer is formed by chemical vapor deposition.
Claim 22
Dependent Claim
16 words
The method of Claim 14, characterized in that the second conductive layer is a metal layer.
Claim 23
Dependent Claim
18 words
The method of Claim 1, characterized in that the second conductive layer is formed by chemical vapor deposition.
Claim 24
Dependent Claim
58 words
The method of Claim 17, characterized in that vias of different depths are formed by plasma etching ) through the remainder of said first insulating layer to said first conductive layer and to active areas of said semiconductor body, and said second conductive layer is of a thickness sufficient to at least partially fill all of the vias.
Claim 25
Dependent Claim
16 words
The method of Claim 22, characterized in that the first conductive layer is a metal layer.
Claim 26
Dependent Claim
37 words
The method of Claim 21, characterized in that the second conductive layer is a layer of a metal or a metal silicide selected from the group consisting of tungsten, aluminium, W silicide, Ti silicide and mixtures thereof.
Claim 27
Dependent Claim
37 words
The method of Claim 23, characterized in that the second conductive layer is a layer of a metal or a metal silicide selected from the group consisting of tungsten, aluminium, W silicide, Ti silicide, and mixtures thereof.
Claim 28
Dependent Claim
58 words
The method of Claim 20, characterized in that vias of a different depth are formed by plasma etching through the remainder of said first insulating layer to said first conductive layer and to active areas of said semiconductor body, and said second conductive layer is of a thickness sufficient to at least partially fill all of said vias.
Claim 29
Dependent Claim
26 words
The method of Claim 26, characterized in that the first conductive layer is a metal layer, an electrically conductive polysilicon layer or a metal silicide layer.
Claim 30
Dependent Claim
31 words
The method of Claim 27, characterized in that the second conductive layer is a layer of a metal selected from the group consisting of tungsten, aluminium, titanium and the metal silicides.
Claim 31
Dependent Claim
223 words
A manufacturing method for providing a semiconductor device with an insulating layer having a generally planar surface and planar contacts, said device comprising a semiconductor body provided with laterally electrically isolated active areas and a first overlying patterned conductive layer, characterized in that the method comprises the steps of: forming a first insulating layer having a generally planar upper surface, on said first conductive layer; forming at least one via to said first conductive layer on to an active area by plasma etching through said first insulating layer down to said first constructive layer or to one of said active areas; forming on the generally planar upper surface of said first insulating layer, a second conductive layer of a thickness sufficient to at least partially fill said via; forming on said second conductive layer a planarizing-iayer having a generally planar upper surface; exposing at least part of said second conductive layer by etching said planarizing layer with etchant that attacks material of said planarizing layer at a significantly greater rate than material of said second conductive layer; and then etching said planarizing layer and said second conductive layer, as it becomes exposed, with etchant that attacks material of said second conductive layer and material of said planarizing layer at substantially equal rates until the upper surface of said first insulating layer is exposed.
Claim 32
Dependent Claim
223 words
A manufacturing method for providing a semiconductor device with an insulating layer having a generally planar surface and planar contacts, said device comprising a semiconductor body provided with laterally electrically isolated active areas and a first overlying patterned conductive layer, characterized in that the method comprises the steps of: forming a first insulating layer having a generally planar upper surface, on said first conductive layer; forming at least one via to said first conductive layer on to an active area by plasma etching through said first insulating layer down to said first constructive layer or to one of said active areas; forming on the generally planar upper surface of said first insulating layer, a second conductive layer of a thickness sufficient to at least partially fill said via; forming on said second conductive layer a planarizing-iayer having a generally planar upper surface; exposing at least part of said second conductive layer by etching said planarizing layer with etchant that attacks material of said planarizing layer at a significantly greater rate than material of said second conductive layer; and then etching said planarizing layer and said second conductive layer, as it becomes exposed, with etchant that attacks material of said second conductive layer and material of said planarizing layer at substantially equal rates until the upper surface of said first insulating layer is exposed.
Claim 33
Dependent Claim
37 words
The method of Claim 7, characterized in that the etch rate of the anisotropic etch forming said via is significantly greater for the material of said first insulating layer than for the material of said semiconductor body.
Claim 34
Dependent Claim
37 words
The method of Claim 8, characterized in that the etch rate of the anisotropic etch forming said via is significantly greater for the material of said first insulating layer than for the material of said semiconductor body.
Claim 35
Dependent Claim
37 words
The method of Claim 9, characterized in that the etch rate of the anisotropic etch forming said via is significantly greater for the material of said first insulating layer than for the material of said semiconductor body.
Claim 36
Dependent Claim
37 words
The method of Claim 10, characterized in that the etch rate of the anisotropic etch forming said via is significantly greater fbr the material of said first insulating layer than for the material of said semiconductor body.
References Cited (Backward Citations)
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