Patent EP0176464A2 successfully refreshed from Google Patents.
EP0176464A2
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Modular multi-channel clock synchronizer
Assignee: RTX Corp
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Filing: 1985-08-29
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Granted: —
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Expires: 2005-08-29
Abstract
Abstract A modular synchronizer for use in synchronizing individual signal processors in a multiprocessor system is disclosed. Each synchronizer has a counter for counting its associated processor's clock pulses and, upon reaching a selected count, providing a counter frame output signal at an output thereof for use by each of the other synchronizers in the system. Each synchronizer has a voter responsive to counter output signals from each of the other synchronizers, and from itself as well, at input ports thereof. Each synchronizer's voter provides a frame sync (macro sync) pulse in each counter frame after receiving a selected number of counter frame output signals from any of the synchronizers in the system. Each synchronizer's voted frame sync pulse is provided at an output port of the synchronizer and may be utilized, depending on the application, for routing back into the synchronizer at a frame sync input port for resetting the synchronizer at a frame sync input port for resetting the synchronizer's counter, or for routing to one or more (slave) synchronizers for the same purpose. Each synchronizer's voter includes a rising edge voter that arms a falling edge voter only during a selected portion of the expected counter frame period (voting window). The synchronizer voter architecture can include clocked latches or not. The synchronizer may include fast and slow clock detectors. The synchronizer interfaces with its associated processor and includes disable circuitry for permitting the CPU to disable nonfunctional frame sync signals.
Inventors
- 👤 Bhalchandra R. Tulpule
- 👤 Edward M. Oscarson
- 👤 David J. Vosgien
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 08:52
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/18; G06F11/187; G06F11/1675; G06F11/1679; G06F11/1691; G06F11/1604
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
192 words
A modular synchronizer for use in a multi-processor system, each processor having an associated oscillator for providing clock pulse signals at a selected frequency and each processor having at least one such modular synchronizer associated therewith, said modular synchronizer comprising: counter means, responsive to the clock pulse signals for counting clock pulses and providing output signal pulses at a selected frame frequency upon reaching a selected count, said frame frequency being the quotient of the selected frequency divided by said selected count; and voter means, responsive to a plurality of incoming counter output signal pulses from a corresponding plurality of the modular synchronizers in the system, for providing a voted frame sync signal pulse at said selected frame frequency at an output port of said modular synchronizer, said modular synchronizer being responsive at an input port thereof to a voted frame sync signal from a selected modular synchronizer in the multi-processor system for resetting the count of said counter means in the presence of a selected number of counter pulses received in each frame period by said selected modular synchronizer, one pulse received from each of said selected number of modular synchronizers.
Claim 2
Dependent Claim
192 words
A modular synchronizer for use in a multi-processor system, each processor having an associated oscillator for providing clock pulse signals at a selected frequency and each processor having at least one such modular synchronizer associated therewith, said modular synchronizer comprising: counter means, responsive to the clock pulse signals for counting clock pulses and providing output signal pulses at a selected frame frequency upon reaching a selected count, said frame frequency being the quotient of the selected frequency divided by said selected count; and voter means, responsive to a plurality of incoming counter output signal pulses from a corresponding plurality of the modular synchronizers in the system, for providing a voted frame sync signal pulse at said selected frame frequency at an output port of said modular synchronizer, said modular synchronizer being responsive at an input port thereof to a voted frame sync signal from a selected modular synchronizer in the multi-processor system for resetting the count of said counter means in the presence of a selected number of counter pulses received in each frame period by said selected modular synchronizer, one pulse received from each of said selected number of modular synchronizers.
Claim 3
Dependent Claim
114 words
The synchronizer of claim 1, wherein said voter means further comprises: rising edge voter means, responsive to the rising edges of said counter output pulses and responsive to the rising edges of said plurality of incoming counter pulses, each for providing a voted arm signal in a frame period in the presence of said selected number of rising edges; and falling edge voter means, responsive to the falling edges of said counter output pulses, and responsive to the falling edges of said plurality of incoming counter pulses, and responsive to said voted arm signal, for providing said voted frame sync signal only after being enabled in said frame period by said voted arm signal.
Claim 4
Dependent Claim
147 words
The synchronizer of claim 1, further comprising: CPU buffer means, responsive to said counter means' output pulses and to said plurality of incoming counter pulses for providing said counter means' output pulses and said plurality of incoming counter pulses at an output port of said synchronizer for use by the processor associated with said synchronizer in detecting nonfunctional counter output signal pulses; CPU latch means, responsive to a disable signal provided by said associated processor in response to the detection by said associated processor of a nonfunctional counter output signal, said disable signal provided to said synchronizer at an input port thereof; and disable gating means, responsive to said counter means' output signal pulses, to said incoming signal pulses and to said disable signal for disabling said nonfunctional signal in the presence of said disable signal by preventing said voter means from receiving. said nonfunctional signal pulses.
Claim 5
Dependent Claim
74 words
The synchronizer of claim 3, wherein said voter further comprises vote select means, responsive to a vote select signal, indicative of said selected number, said vote select signal provided by said processor to said CPU latch means, wherein said processor may change the magnitude of said vote select signal to become indicative of another selected number lesser than said selected number, in response to said detection of a nonfunctional counter signal in the system.
Claim 6
Dependent Claim
92 words
The synchronizer of claim 1, wherein said voter means further comprises: latch means, responsive to said counter means' output pulses and to said plurality of incoming counter pulses, for synchronously providing in each frame period, latched signals indicative of the states of said counter means' output pulses in each frame period and the states of said incoming counter pulses in each frame period; and gating means, responsive to said latched signals for providing said voted frame sync signal in the presence of said selected number of latched signals in each frame period.
Claim 7
Dependent Claim
112 words
The synchronizer of claim 1, wherein said voter means further comprises: ones adder means, responsive to said counter means' output pulses and to said plurality of incoming counter pulses for providing an adder output signal indicative of said selected number of counter pulses received in a frame; and logic means, responsive to said adder output signal and to a vote select signal indicative of said selected number, said select signal provided by said associated processor, said logic means comparing said adder output signal to said vote select signal and providing said frame sync signal only if the number of counter pulse in a frame is greater or equal to said selected number.
Claim 8
Dependent Claim
121 words
The synchronizer of claim 1, wherein said voter means further comprises: ones adder means, responsive to said counter means' output pulses and to said plurality of incoming counter pulses for providing an adder output signal indicative of the number of enabled counter output signals in a frame; and magnitude comparator means, responsive to said adder output signal and to a vote select signal indicative of said selected number from said associated processor for comparing said adder output signal to said vote select signal and providing said frame sync signal only if the number of enabled counter output signals, of which said adder output signal is indicative, is greater or equal to said selected number as indicated by said vote select signal.
Claim 9
Dependent Claim
46 words
The synchronizer of claim 1, further comprising: fast sync pulse detector means, responsive to said synchronizer's counter means' output signal pulses for detecting an increase in said frame frequency and providing a fast sync pulse interrupt signal indicative thereof to the processor associated with said synchronizer.
Claim 10
Dependent Claim
46 words
The synchronizer of claim 1, further comprising: slow sync pulse detector means, responsive to said synchronizer's counter means' output signal pulses for detecting a decrease in said frame frequency and providing a slow sync pulse interrupt signal indicative thereof to the processor associated with said synchronizer.
Claim 11
Dependent Claim
59 words
The synchronizer according to claim 1, further comprising: plural counter output signal ports, each responsive to said counter means' output signal, each port providing said counter output signal at an isolated output thereof; and plural counter input signal ports, each responsive at an isolated input thereof, to incoming counter output signals from any of the synchronizers in the system.
Claim 12
Dependent Claim
66 words
The synchronizer according to claim 1, further comprising, voter enabler means, responsive to count signals generated by said counter, said count signals being indicative of the present count of said counter means, for providing a voter enable signal to said voter means during a timed portion of each frame period during which timed portion said synchronizer's counter means is expected to provide an output signal pulse.
Claim 13
Dependent Claim
193 words
A synchronizer for use in a multi-processor system, each processor having an associated oscillator for providing clock pulse signals at a selected frequency and each processor having at least one such synchronizer associated therewith, said synchronizer comprising: counter means, responsive to the clock pulse signals for counting clock pulses and providing output signal pulses at a selected frame frequency upon reaching a selected count, said frame frequency being the quotient of the selected frequency divided by said selected count; and voter means, responsive to said output signal pulses from said counter means, and responsive to a plurality of incoming counter output signals pulses one from each of the synchronizers in the system, for providing a voted frame sync signal pulse at said selected frame frequency for resetting the count of said counter means in the presence of a selected number of counter pulses received in each frame period, one pulse from each of said selected number of synchronizers which number may include any of the synchronizers in the system in any combination and in any sequence, said seleced number being less than or equal to the total number of synchronizers in the system.
Claim 14
Dependent Claim
193 words
A synchronizer for use in a multi-processor system, each processor having an associated oscillator for providing clock pulse signals at a selected frequency and each processor having at least one such synchronizer associated therewith, said synchronizer comprising: counter means, responsive to the clock pulse signals for counting clock pulses and providing output signal pulses at a selected frame frequency upon reaching a selected count, said frame frequency being the quotient of the selected frequency divided by said selected count; and voter means, responsive to said output signal pulses from said counter means, and responsive to a plurality of incoming counter output signals pulses one from each of the synchronizers in the system, for providing a voted frame sync signal pulse at said selected frame frequency for resetting the count of said counter means in the presence of a selected number of counter pulses received in each frame period, one pulse from each of said selected number of synchronizers which number may include any of the synchronizers in the system in any combination and in any sequence, said seleced number being less than or equal to the total number of synchronizers in the system.
References Cited (Backward Citations)
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