Patent EP0176409A2 successfully refreshed from Google Patents.
EP0176409A2
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Cmos circuit having a reduced tendency to latch
Assignee: Fairchild Semiconductor Corp
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Filing: 1985-09-05
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Granted: —
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Expires: 2005-09-05
Abstract
Abstract The tendency of a CMOS circuit to latch up is reduced by implanting ions of germanium or tin into the source and drain regions of the circuit. The low energy gap of these ions lowers the band gap of the source and drain regions, which in turn inhibits their ability to inject carriers into the substrate and well.
Inventors
- 👤 Robert Strain
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 06:07
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/80; H10D62/83; H10D62/834; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854; H10P30/208; Y; Y10; Y10S; Y10S148/00; Y10S148/061; Y10S438/00; Y10S438/914; Y10S438/918
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
67 words
In a CMOS integrated circuit comprising complementary NMOS and PMOS transistors formed on a substrate, a method for reducing the tendency of the circuit to latch comprising the step of implanting ions into the source region of each of the NMOS and PMOS transistors, said ions being of a material having an energy gap which is lower than the energy gap of the material forming the substrate.
Claim 2
Dependent Claim
67 words
In a CMOS integrated circuit comprising complementary NMOS and PMOS transistors formed on a substrate, a method for reducing the tendency of the circuit to latch comprising the step of implanting ions into the source region of each of the NMOS and PMOS transistors, said ions being of a material having an energy gap which is lower than the energy gap of the material forming the substrate.
Claim 3
Dependent Claim
26 words
The method of claim 1 wherein ions of said lower energy gap material are also implanted into the drain regions of said NMOS and PMOS transistors.
Claim 4
Dependent Claim
20 words
The method of claim 1 wherein the substrate is made of silicon and said lower energy gap material is germanium.
Claim 5
Dependent Claim
20 words
The method of claim 1 wherein the substrate is made of silicon and said lower energy gap material is tin.
Claim 6
Dependent Claim
132 words
In a CMOS integrated circuit comprising a substrate of one conductivity, a source and a drain each of a conductivity opposite to said one conductivity formed in said substrate, a well of said opposite conductivity formed in said substrate and a source and a drain of said one conductivity formed in said well, a method for reducing the tendency of the circuit to latch up comprising the steps of modifying the energy gap of one of said substrate and said source of said opposite conductivity so that the energy gap of said source is less than that of said substrate, and modifying the energy gap of one of said well and said source of said one conductivity so that the energy gap of said source is less than that of said well.
Claim 7
Dependent Claim
132 words
In a CMOS integrated circuit comprising a substrate of one conductivity, a source and a drain each of a conductivity opposite to said one conductivity formed in said substrate, a well of said opposite conductivity formed in said substrate and a source and a drain of said one conductivity formed in said well, a method for reducing the tendency of the circuit to latch up comprising the steps of modifying the energy gap of one of said substrate and said source of said opposite conductivity so that the energy gap of said source is less than that of said substrate, and modifying the energy gap of one of said well and said source of said one conductivity so that the energy gap of said source is less than that of said well.
Claim 8
Dependent Claim
32 words
The method of claim 5 wherein said modifying steps comprise implanting said sources with ions of a material having a lower energy gap than the material forming said substrate and said well.
Claim 9
Dependent Claim
81 words
A CMOS integrated circuit having a reduced tendency to latch up, comprising: a substrate of one conductivity; a source and a drain of opposite conductivity formed in said substrate, at least said source having an energy gap lower than that of said substrate; a well of said opposite conductivity formed in said substrate; and an source and a drain of said one conductivity formed in said well, at least said source having an energy gap lower than that of said substrate.
Claim 10
Dependent Claim
81 words
A CMOS integrated circuit having a reduced tendency to latch up, comprising: a substrate of one conductivity; a source and a drain of opposite conductivity formed in said substrate, at least said source having an energy gap lower than that of said substrate; a well of said opposite conductivity formed in said substrate; and an source and a drain of said one conductivity formed in said well, at least said source having an energy gap lower than that of said substrate.
Claim 11
Dependent Claim
27 words
The integrated circuit of claim 7 wherein both of said source and drain of said opposite conductivity have an energy gap lower than that of said substrate.
Claim 12
Dependent Claim
27 words
The integrated circuit of claim 7 wherein both of said source and drain of said one conductivity have an energy gap lower than that of said well.
References Cited (Backward Citations)
No citation records indexed.
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