Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
194 words
A video signal memory for storing n 2 m video data words, the memory being characterised by: an arra) (21) of n by n memory modules (22) each capable of storing m said video data words corresponding respectively to sample values at respective sample positions of a raster display; a first group of buses (41) for supplying data and address signals to the n columns respectively of said array (21); a second group of n buses (42) for supplying data and address signals to the n rows respectively of said array (21); and means (43, 44, 49, 50) selectively to enable said first or said second group of buses (41, 42) in each write cycle of said video signal memory and in said write cycle to supply over the enabled said group of buses (41, 42) up to n said data and address signals respectively, the address in each said data and address signal designating the address in a said memory module (22) where said data is to be stored, and the data in the said data and address signal being the data to be stored at said address in said memory module (22).
Claim 2
Dependent Claim
194 words
A video signal memory for storing n 2 m video data words, the memory being characterised by: an arra) (21) of n by n memory modules (22) each capable of storing m said video data words corresponding respectively to sample values at respective sample positions of a raster display; a first group of buses (41) for supplying data and address signals to the n columns respectively of said array (21); a second group of n buses (42) for supplying data and address signals to the n rows respectively of said array (21); and means (43, 44, 49, 50) selectively to enable said first or said second group of buses (41, 42) in each write cycle of said video signal memory and in said write cycle to supply over the enabled said group of buses (41, 42) up to n said data and address signals respectively, the address in each said data and address signal designating the address in a said memory module (22) where said data is to be stored, and the data in the said data and address signal being the data to be stored at said address in said memory module (22).
Claim 3
Dependent Claim
26 words
A video signal memory according to claim 1 wherein each said bus in each said group of buses (41, 42) comprises a buffer circuit (43, 44).
Claim 4
Dependent Claim
50 words
A video signal memory according to claim 2 wherein said first or said second group of buses (41, 42) is enabled by supplying an enable signal to the n said buffer circuits (43, 44) in the said first or second group of buses (41, 42) which is to be enabled.
Claim 5
Dependent Claim
24 words
A video signal memory according to claim 1, claim 2 or claim 3 wherein each said memory module (22) is a random access memory.
Claim 6
Dependent Claim
18 words
A video signal memory according to any one of the preceding claims wherein n is equal to 8.
Claim 7
Dependent Claim
27 words
A video signal memory according to any one of the preceding claims for use in a high definition video system and wherein m is equal to 16K.
Claim 8
Dependent Claim
25 words
A video signal memory according to any one of the preceding claims forming part of a special effects equipment in a high definition video system.