Wafer scale integrated circuit device

Claim 2

A hybrid integrated circuit system having an array of integrated circuit chip dice (10', 24,25) disposed on a monolithic silicon wafer substrate for intercorrection into a complex array of electronic circuit elements; characterized in that the monolithic wafer has in two planes patterned metal (19,20) separated except at a connection point by an insulator (21,22) for providing a plurality of horizontally and vertically disposed logic network lines (9,10) disposed to run across the wafer and a plurality of horizontally and vertically disposed bonding pad lines (6,7) which have a bonding pad (8,14,15) disposed on the top surface of the wafer to define a bonding position in bonding cell areas (2,3) on the surface of the wafer which bonding pad is connected to its corresponding bonding pad line (6,7), in that a plurality of bonding pads define a cell location (23) at which said chip dice (10',24,25), each having its own plurality of bonding pads are bonded to the top surface of the monolithic wafer (1) with their backs bonded to the wafer to form a wafer-chip sandwich, with insulation bonding material therebetween, and in that bonding wire connections are made between the logic bonding pads on said chip die (10', 24,25) and the bonding pads (8,14,15) on the wafer.

Claim 3

A hybrid integrated circuit system according to claim 1 characterized in that said monolithic wafer (1) has formed on a base substrate thereof a first conductive interconnection layer of lines and a second conductive interconnection layer of lines and a layer of insulation separating said first and second interconnection layers, said base substrate being adapted for carrying a plurality of integrated circuit chips above said layers, and said first and second interconnection layers being adapted to provide a routing network capable of handling many independent and concurrent signals between said integrated circuit chips which are to be mounted on said substrate by a discretionary pattern of interconnection lines, said first and second interconnection layers being interconnected by vias passing through selected cross points of an insulating layer separating said interconnection layers, each of which vias connects a line in said first interconnection layer with a line in said second interconnection layer to complete and fix a discretionary pattern of interconnection lines, each of said discretionary cross-points being a bi-directional conductive via to form at least a part of said discretionary pattern of interconnection lines for said integrated circuit chips.

Claim 4

A hybrid integrated circuit system according to claim 1 characterized by: a monolithic wafer substrate (1), a reticulate network (11') deposited on said wafer substrate including a plurality of net lines (9) aligned in a first direction and another plurality of net lines (10) aligned in a second direction, said network having a plurality of network lines, each having a test pad terminal (16', 18', 20', 13'), formed by having single ones of said net lines aligned in a first direction permanently connected to a corresponding net line of the lines aligned in a second direction enabling bi-directional current flow from the first net line to the second net line and from the second net line to the first net line at least some of said network lines being disconnected from other elements formed on said substrate, a plurality of pad lines (6, 7), said pad lines crossing net lines but being normally insulated therefrom, a plurality of bonding pads (8) located on the surface of said substrate, said bonding pads being connected each to a single pad line (6, 7), a plurality of via interconnection means (17) for permitting discretionary interconnection of a first bonding pad (8) through a selected network line (9, 10, 11') to a second bonding pad (8) each consisting of: (a) a first pad line which crosses a discretionary network line at a first point, (b) a second pad line which crosses said discretionary network line at a second point, (c) said via means (17) intercoupling a pad line (6, 7) to a network (11') so as to permit bidirectional conduction between said first bonding pad (8) and said second bonding pad (8).

Claim 5

A hybrid integrated circuit system according to claim 1 for interconnecting a plurality of integrated circuit chips which are to be mounted on a monolithic wafer substrate, the substrate comprising, a silicon wafer substrate having formed thereon a plurality of net conductors in a reticulate array network (11') of similar net conductors (6, 7) which when interconnected to integrated circuits mounted on said substrate form a bi-directional routing network for the many concurrent chip-to-chip signals traveling through said network, means for defining which of the similar net conductors of the reticulate array network carry signals for which chips, said defining means including a plurality of contact pads for chips located on the surface of said substrate at spaced distances which permit a bonding of a great variety of different sized and/or function chips to be bonded to said pads and associated pad lines for each contact pad traveling across the network, and interconnection vias (28, 16, 17) between a pad line and a single one of the associated net conductors of the network and between another pad line and said single one of the associated net conductors of the networks whereby communication between pad lines is made through the reticulate array network by the net conductor which has via interconnection of the pad lines and selected associated net conductors.

Claim 6

A hybrid integrated circuit system according to claim 1 characterized in that said reticulate network (11') is composed of an array of net conductors as a first plurality of net lines deposited on the substrate traveling in a first direction and a second plurality of net lines deposited on the substrate traveling in a second direction, each of the lines of the first direction being permanently connected through a mask formed permanent via to at least a corresponding one of the lines traveling in a second direction to form a first of a plurality of possible networks, the connection of pad lines to their associated one of the net lines forming a conductive via, one pad line to one net conductor, and defining the desired and discretionary interconnection through the network of interconnected lines which are connected to different contact pads.

Claim 7

A hybrid integrated circuit system formed in combination with a monolithic wafer interconnection substrate according to claim 18 characterized by: a silicon wafer support substrate element of said wafer having formed thereon a conductive grounding layer; and also having thereon an insulation layer carrying in two layers a reticulate array of conductors; said reticulate array of conductors having a first plurality of logic net lines and a second plurality of logic net lines arranged in substantially parallel but orthogonal directions on said insulation layer and having points of interconnection at crossing points between lines of said first and second plurality of logic net lines, a plurality of contact pads on the surface of said wafer with pad lines being connected to each of the contact pads, said pad lines crossing said array of conductors at a plurality of points but each being connected to only one associated logic net line if connected at all by a via connection (16, 17, 28), thereby defining a bi-directional routing connection for signals between selected contact pads on the surface of the said substrate and its associated logic line, and a like pad to logic line connection being formed to complete a pad through logic line to pad connection, power distribution means having power hook-up areas across the surface of said substrate and including power hook-up pads located on the surface of the substrate, and integrated circuits of different functions located on the surface of said substrate and having their bonding pads connected to the said contact pads on the surface of said substrate, the routing network between chips being defined after manufacture of said universal interconnection support substrate.

Claim 8

A hybrid integrated circuit system according to claim 1 characterized in that a test pad terminal of a net line is located at the periphery of the substrate.

Claim 9

A hybrid integrated circuit system according to claim 1 characterized by net line terminals (16', 20', 13') which serve as input/output ports for the system formed by interconnected chips.

Claim 10

A hybrid integrated circuit system according to claim 1 characterized in that chip bonding pads are distributed in a regular pattern across the substrate and terminals are distributed in a regular pattern about the periphery of the substrate.

Claim 11

A hybrid integrated circuit system according to claim 1 characterized in that there is provided a two rail power distribution matrix wherein a possible integrated circuit bonding area of the substrate is crossed by both rails, each power rail being connected to a pair of contact pads in a power hookup area.

Claim 12

A hybrid integrated circuit system according to claim 1 characterized in that two power rails for the integrated circuits pass along the edges and along the center lines of a possible integrated circuit bonding area of the substrate.