Content addressable memory cell

Claim 2

A content addressable memory cell characterized by: an MOS memory cell coupled to two bit lines and having two signal nodes which are only stable in opposite logical states, said logical states indicating the data stored in said MOS memory cell; a flag line for carrying a match signal consisting of voltage variations indicating a match or no match condition between data presented on said bit lines and data stored in said cell; and associative means coupled to said bit lines, said MOS memory cell signal nodes and said flag line for comparing the data on said bit lines to the data stored in said cell and for causing voltage variation on said flag line to indicate either a match or no match condition.

Claim 3

The memory cell of claim 1 characterized in that said MOS memory cell includes means to allow normal read and write random access to the memory cell.

Claim 4

The memory cell of claim 1 or 2 characterized in that said associative means includes a separate flag line and word line.

Claim 5

The memory cell of claim 1, 2 or 3 characterized by a flag driver means to alternatively couple said flag line to a predetermined source of bias voltage or leave the flag line uncoupled to any other bias voltage source such that it can maintain its current signal voltage level depending upon the match or mismatch state of the data on the bit lines compared to the data stored in said MOS memory cell.

Claim 6

The memory cell of claim 4 characterized in that said flag driver means is an MOS transistor having a gate terminal connected to a flag node which is either charged or discharged by means for comparing data on said bit lines to data stored in said MOS memory cell.

Claim 7

The memory cell of claim 4 characterized in that said comparing means includes an MOS transistor having its gate coupled to said interrogate line and its source and drain terminals coupled between said flag node and a voltage source.

Claim 8

The memory cell of any one of claims 1-6 characterized in that each said signal node of said MOS memory cell is individually coupled to one of the gates of said first and second MOS transistors included in said comparing means.

Claim 9

The memory cell of claim 5, 6 or 7 characterized in that said flag noae is coupled to a bias voltage through either of two switching branches.

Claim 10

The memory cell of claim 8 characterized in that each of said switching branches contains one of said first or second MOS transistors and an additional MOS transistor having its source and drain coupled between said flag node and said first or said second MOS transistor, said additional MOS transistor having its gate terminal coupled to one of said bit lines.

Claim 11

The memory cell of claim 1 characterized in that said associative means includes: an MOS transistor biased into its non-saturated region coupled between a first bias voltage source and a flag node to cause said flag node to be biased to a predetermined voltage; switch path means for conditionally coupling said flag node to a second bias voltage source through either two parallel paths to said second bias voltage source so as to alter the bias voltage on said flag node or leave the bias voltage on said flag node unchanged depending upon the matched or unmatched state of the data on said signal nodes compared to the data on said bit lines; and flag line driver means coupled between said flag node and said flag line for either altering or leaving unchanged the bias voltage level on said flag line depending upon the state of the bias voltage on said flag node.

Claim 12

ll. The memory cell of claim 1 characterized in that said associative means includes: an MOS transistor coupled between a first bias voltage source and a flag node said transistor biased into the saturation region so as to cause said flag noae to biased at a predetermined voltage level; switching path means for conditionally coupling said flag node to a second bias voltage source through either of two parallel paths to said second bias voltage source so as to alter the bias voltage on said flag node or leave the bias voltage on said flag node unchanged depending upon the matched or unmatched state of the data on said signal nodes compared to the data on said bit lines; and flag line driver means coupled between said flag node and said flag line for either altering or leaving unchanged the bias voltage level on said flag line depending upon the state of the bias voltage on said flag node.

Claim 13

The memory cell of claim 10 or 11 characterized in that said switching path means is comprised of two branches between said flag node and said second bias voltage source, each said branch comprised of a first MOS transistor having its drain coupled to said flag node and its gate coupled to one of said bit lines and its source coupled to the drain of a second MOS transistor which has its gate coupled to one of said signal nodes and its source coupled to said second bias voltage source.

Claim 14

The memory cell of claim 10 or 11 characterized in that said switching path means comprises two NAND gates each having its output coupled to said flag node and each having one input coupled to one of said bit lines and the other input coupled to one of said signal nodes.

Claim 15

A content addressable memory cell characterized by: an MOS memory cell coupled to two bit lines, a word/flag line and an interrogate line said memory cell for storing data; an associative memory means coupled to said MOS memory cell, said bit lines, said word/flag line and said interrogate line for comparing data storea in said MOS memory cell to data present on said bit lines and for causing the voltage on said word/flag line to change for a predetermined state of match or mismatch between the data compared.

Claim 16

A content addressable memory cell characterized by: an MOS memory cell coupled to two bit lines, a word/flag line and an interrogate line said memory cell for storing data; an associative memory means coupled to said MOS memory cell, said bit lines, said word/flag line and said interrogate line for comparing data storea in said MOS memory cell to data present on said bit lines and for causing the voltage on said word/flag line to change for a predetermined state of match or mismatch between the data compared.

Claim 17

The memory cell of claim 14 characterized in that said associative memory means comprises: an MOS transistor having its gate coupled to said interrogate line and having its source and drain coupled between a first bias voltage source and a flag node to cause said flag node to be biased to a predetermined voltage upon a predetermined condition of said interrogate line; switching path means for conditionally coupling said flag node to a second bias voltage source through either of two parallel paths to said second bias voltage source so as to alter the bias voltage on said flag noae or leave the bias voltage on said flag node unchanged depending upon the matched or unmatched state of the data on said signal nodes compared to the data,on saia bit lines; word/flag line driver means coupled between said flag node and said word/flag line for causing a predetermined change in the bias voltage level on said word/flag line depending upon the state of the bias voltage on said flag node; and multiplexer means coupled to said word/flag line for causing it to function as a normal word line in a static RAM cell during normal random access read or write operations but to cause said word line to act as a flag line during associative memory operations.