Dynamic random access memory (dram)

Claim 1

A three-transistor cell for a dynamic random access memory formed on a semiconductor substrate (1), the cell comprising a read select transistor (T₁), having a drain (3a) connected to a data bit line (DL) of the memory, and a gate (5, 15) connected to a read select line (RL, WRL) of the memory, a storage transistor (T₃), having a drain (Ch1) connected to a source (Ch3) of the read select transistor (T₁) and a source (3b) connected to a ground line (GND) of the memory, and a write select transistor (T₂) having a source (9b) connected to a gate (9b) of the storage transistor, a gate (11, 15) connected to a write select line (WL, WRL) of the memory, and a drain (9a) connected to the data bit line (DL), characterised in that the read select transistor (T₁) and the storage transistor (T₃) are formed as a dual gate transistor (T₁, T₃; T d ), a channel region (Ch1) of the read select transistor being directly connected to a channel region (Ch3) of the storage transistor to provide a channel region (Ch2, Ch3) of the dual gate transistor, the channel region (Ch1) of the read select transistor also acting as drain of the storage transistor and the channel region (Ch3) of the storage transistor also acting as source of the read select transistor, the drain (3a) of the read select transistor being the drain of the dual gate transistor and the source (3b) of the storage transistor being the source of the dual gate transistor, between which drain (3a) and source (3b) the channel region (Ch1, Ch3) of the dual gate transistor lies, and the two gates of the dual gate transistor being, respectively, the gate (5; 15) of the read select transistor and the gate (9b) of the storage transistor, which gates overlie the channel region (Ch1, Ch3) of the dual gate transistor via an interposed insulator layer (4, 7), and characterised in that the write select transistor (T₂) is formed over the read select transistor (T₁), with an interposed insulator layer (6, 7; 6, 7, 10), the drain (9a) of the write select transistor being connected directly to the drain (3a) of the read select transistor through a window or opening in the latter interposed insulator layer, and in that the source region (9b) of the write select transistor (T₂) acts also as the gate of the storage transistor (T₃) which is otherwise provided on the same side of the latter interposed insulator layer as the read select transistor.