Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
179 words
In an automatic test system for the testing of an integrated circuit in a test head, the system controlled by a data processing unit aαd including a timing subsystem for providing timing signals including a cyclical test period clock signal, a formatting circuit characterized by: operating mode register means coupled to the data processing unit for storing data received therefrom indicative of a test to be performed; test head controller means coupled to the operating mode register means and to the timing subsystem for controlling the test head in response to the state of the operating mode register means, the test head controller means including means for supplying stimuli signals to the test head during a test period cycle subsequent to the test period cycle from which the stimuli signals originated; and error correlator means coupled to receive tne timing signals from the timing subsystem, coupled to the register means and coupled to receive response signals from the test head, the error correlator means for associating the response signals with the test period from whicn the stimuli signals originated.
Claim 2
Dependent Claim
179 words
In an automatic test system for the testing of an integrated circuit in a test head, the system controlled by a data processing unit aαd including a timing subsystem for providing timing signals including a cyclical test period clock signal, a formatting circuit characterized by: operating mode register means coupled to the data processing unit for storing data received therefrom indicative of a test to be performed; test head controller means coupled to the operating mode register means and to the timing subsystem for controlling the test head in response to the state of the operating mode register means, the test head controller means including means for supplying stimuli signals to the test head during a test period cycle subsequent to the test period cycle from which the stimuli signals originated; and error correlator means coupled to receive tne timing signals from the timing subsystem, coupled to the register means and coupled to receive response signals from the test head, the error correlator means for associating the response signals with the test period from whicn the stimuli signals originated.
Claim 3
Dependent Claim
52 words
Apparatus as in claim 1 characterized in tnat the test head comprises: driver means switchaoly connectable to the integrated circuit for applying stimuli signals to input nodes of the integrated circuit; and comparator means switchably connectable to the integrated circuit for receiving response signals from the output nodes of the integrated circuit.
Claim 4
Dependent Claim
24 words
Apparatus as in claim 1 or 2 characterized in that the test head controller means controls both the driver means and the comparator means.
Claim 5
Dependent Claim
60 words
Apparatus as in claim 1, 2 or 3 characterized in that the register means comprises: driver format register means for storing data indicative of a format of a stimuli signal to be supplied by the driver means; and comparator format register means for storing data indicative of a format of a response signal to be received by the comparator means.
Claim 6
Dependent Claim
36 words
Apparatus as in claim 4 characterized in that the register means further comprises resource allocation means for storing data indicative of the driver and comparator means to be coupled to a node of the integrated circuit.
Claim 7
Dependent Claim
54 words
Apparatus as in claim 1, 2, 3 or 4 characterized in that the timing subsystem further supplies to the formatting circuit a test subcycle clock occurring at least once per test period and a leading edge signal to define the time at which a stimuli signal is to be applied to the integrated circuit.
Claim 8
Dependent Claim
32 words
Apparatus as in claim 4 further characterized by test vector generating means, coupled to the test head controller means, for storing data to be used in the testing of the integrated circuit.
Claim 9
Dependent Claim
67 words
Apparatus as in claim 5 characterized in that the test vector generating means stores data for each node of the integrated circuit comprising: definition data to specify which of the driver means or comparator means will be coupled to said node of the integrated circuit; mask data to specify whether errors detected at said node are to be ignored or not; and test data for said node.
Claim 10
Dependent Claim
49 words
Apparatus as in claim 8 characterized in that the test head controller means further comprises pin multiplexing means responsive to the test vector generating means for combining the data stored in the test vector generating means for two different nodes and using the combined data for a single node..
Claim 11
Dependent Claim
56 words
Apparatus as in claim 9 characterized in that the test head controller means further comprises split pin means for dividing tne data stored in the test vector generating means for a single node and using a first part of the data for a first node and a second part of the data for a second node.
Claim 12
Dependent Claim
60 words
Apparatus as in claim 10 characterized in that the test head controller means further comprises reassignment means for dividing the data stored in the test vector generating means for each of two nodes and using some of the data stored for each node on the first node and some of the data stored for each node on the second node.